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X4043 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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X4043 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 24 page  FN8118 Rev 3.00 Page 1 of 24 December 9, 2015 FN8118 Rev 3.00 December 9, 2015 X4043, X4045 4k, 512 x 8 Bit CPU Supervisor with 4kbit EEPROM DATASHEET FEATURES • Selectable watchdog timer •Low VCC detection and reset assertion —Five standard reset threshold voltages —Adjust low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Low power CMOS —<20µA max standby current, watchdog on —<1µA standby current, watchdog OFF —3mA active current • 4kbits of EEPROM —16-byte page write mode —Self-timed write cycle —5ms write cycle time (typical) • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes of EEPROM array with Block Lock™ protection • 400kHz 2-wire interface • 2.7V to 5.5V power supply operation • Available packages —8 Ld SOIC —8 Ld MSOP —8 Ld PDIP • Pb-free plus anneal available (RoHS compliant) DESCRIPTION The X4043/45 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space require- ments, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscilla- tor to stabilize before the processor can execute code. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry stan- dard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the thresh- old for applications requiring higher precision. BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode & Control Logic SDA SCL VCC Reset & Watchdog Timebase Power-on and Generation VTRIP + - RESET (X4043) Reset Low Voltage Status Register Protect Logic EEPROM Array Watchdog Transition Detector WP VCC Threshold Reset logic RESET (X4045) |
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