X4043 datasheet(13/24 Pages) RENESAS

13 / 24 page

X4043, X4045

FN8118 Rev 3.00

Page 13 of 24

December 9, 2015

Acknowledge Polling

The disabling of the inputs during nonvolatile cycles can

be used to take advantage of the typical 5kHz write cycle

time. Once the stop condition is issued to indicate the

end of the master’s byte load operation, the device initi-

ates the internal nonvolatile cycle. Acknowledge polling

can be initiated immediately. To do this, the master

issues a start condition followed by the slave address

byte for a write or read operation. If the device is still

busy with the nonvolatile cycle then no ACK will be

returned. If the device has completed the write opera-

tion, an ACK will be returned and the host can then pro-

ceed with the read or write operation. Refer to the flow

chart in Figure 13.

Serial Read Operations

Read operations are initiated in the same manner as

write operations with the exception that the R/W bit of

the slave address byte is set to one. There are three

basic read operations: Current Address Reads, Random

Reads, and Sequential Reads.

Current Address Read

Internally the device contains an address counter that

maintains the address of the last word read incremented

by one. Therefore, if the last read was to address n, the

next read operation would access data from address

n+1. On power-up, the address of the address counter is

undefined, requiring a read or write operation for initial-

ization.

Upon receipt of the slave address byte with the R/W bit

set to one, the device issues an acknowledge and then

transmits the eight bits of the data byte. The master termi-

nates the read operation when it does not respond with an

acknowledge during the ninth clock and then issues a

stop condition. Refer to Figure 13 for the address,

acknowledge, and data transfer sequence.

Figure 13. Acknowledge Polling Sequence

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read oper-

ation, the master must either issue a stop condition

during the ninth cycle or hold SDA HIGH during the ninth

clock cycle and then issue a stop condition.

Figure 14. Current Address Read Sequence

ACK

Returned?

Issue Slave Address

Byte (Read or Write)

Byte Load Completed

by Issuing STOP.

Enter ACK Polling

Issue STOP

Issue START

YES

Nonvolatile Cycle

Complete. Continue

Command

Issue STOP

Continue Normal Read

or Write Command

Sequence

PROCEED

YES

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

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