X98021 datasheet(5/29 Pages) RENESAS

5 / 29 page

X98021

FN8219 Rev 3.00

Page 5 of 29

March 8, 2006

tSETUP

DATA valid before rising edge of DATACLK 15pF DATACLK load, 15pF DATA load

(Note 1)

1.3

tHOLD

DATA valid after rising edge of DATACLK

15pF DATACLK load, 15pF DATA load

(Note 1)

2.0

AC TIMING CHARACTERISTICS (2 WIRE INTERFACE)

fSCL

SCL Clock Frequency

400

kHz

Maximum width of a glitch on SCL that will

be suppressed

2 XTAL periods min

tAA

SCL LOW to SDA Data Out Valid

5 XTAL periods plus SDA’s RC time

constant

See

comment

µs

tBUF

Time the bus must be free before a new

transmission can start

1.3

µs

tLOW

Clock LOW Time

1.3

µs

tHIGH

Clock HIGH Time

0.6

µs

tSU:STA

Start Condition Setup Time

0.6

µs

tHD:STA

Start Condition Hold Time

0.6

µs

tSU:DAT

Data In Setup Time

100

tHD:DAT

Data In Hold Time

0ns

tSU:STO Stop Condition Setup Time

0.6

µs

tDH

Data Output Hold Time

4 XTAL periods min

160

NOTES:

1. Setup and hold times are at a 140MHz DATACLK rate.

Electrical Specifications

Specifications apply for VA = VD = VX = 3.3V, pixel rate = 210MHz, fXTAL = 25MHz, TA = 25°C,

unless otherwise noted (Continued)

SYMBOL

PARAMETER

COMMENT

MIN

TYP

MAX

UNIT

tSU:STO

tDH

tHIGH

tSU:ST

tHD:STA

tHD:DAT

tSU:DAT

SCL

SDA IN

SDA OUT

tLOW

tBUF

tAA

FIGURE 1. 2 WIRE INTERFACE TIMING

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