X98021 datasheet(23/29 Pages) RENESAS

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X98021

FN8219 Rev 3.00

Page 23 of 29

March 8, 2006

Crystal Oscillator

An external 23MHz to 27MHz crystal supplies the low-jitter

reference clock to the DPLL. The absolute frequency of this

crystal within this range is unimportant, as is the crystal’s

temperature coefficient, allowing use of less expensive, lower-

grade crystals.

EMI Considerations

There are two possible sources of EMI on the X98021:

• Crystal oscillator. The EMI from the crystal oscillator is

negligible. This is due to an amplitude-regulated, low voltage

sine wave oscillator circuit, instead of the typical high-gain

square wave inverter-type oscillator, so there are no

harmonics. The crystal oscillator is not a significant source of

EMI.

• Digital output switching. This is the largest potential

source of EMI. However, the EMI is determined by the PCB+

layout and the loading on the databus. The way to control

this is to put series resistors on the output of all the digital

pins. These resistor values should be adjusted to optimize

signal quality on the bus. Intersil recommends starting with

 and adjusting as necessary for the particular PCB

layout and device loading.

Recommendations for minimizing EMI are:

• Minimize the databus trace length

• Minimize the databus capacitive loading.

If EMI is a problem in the final design, increase the value of the

digital output series resistors to reduce slew rates on the bus.

This can only be done as long as the scaler’s setup and hold

timing requirements continue to be met.

Alternate Pixel Sampling

Two X98021s (AFEA and AFEB) may be used simultaneously

to achieve effective sample rates greater than 210MHz. Each

AFE is programmed with an HTOTAL value equal to one-half of

the total number of pixels in a line. The CLOCKINVIN pin for

AFEA is tied to ground, AFEB is tied to VD. Both AFEs are

otherwise programmed identically, though some minor phase

adjustment may be needed to compensate for any propagation

delay mismatch between the two AFEs.

The CLOCKINVIN setting shifts the phase of AFEB by 180

degrees from AFEA. AFEA now samples the even pixels on the

rising edge of its DATACLK, while AFEB samples the odd

pixels on the rising edge of its clock. With each AFE in 24 bit

mode, two 24 bit data streams are generated (Figure 9).

With both AFEs configured for 48 bit mode, a 96 bit datastream

is generated (Figure 10).

In both cases, AFEA and AFEB are on different DATACLK

domains. In 24 bit mode, the data from each AFE must be

latched on the rising edge of that AFE’s DATACLK. In 48 bit

mode, the frequencies are low enough that the rising edge of

AFE B can be used to capture both AFEB and AFEA data.

HSYNC

(to A and B)

DATACLK (A)

DATA (A)

OUT (A)

DATACLK (B)

DATA (B)

OUT (B)

DPLL Lock Edge

½ DATACLK Delay

CLKINV

IN (A) = GNDD

CLKINV

IN (B) = VD

N-3

N-1

N-2

N-3 PN-2

N-1

Analog Video In

(to A and B)

FIGURE 9. ALTERNATE PIXEL SAMPLING (24 BIT MODE)

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