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SH7145 Datasheet(PDF) 55 Page - Renesas Technology Corp |
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SH7145 Datasheet(HTML) 55 Page - Renesas Technology Corp |
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55 / 773 page  Rev. 2.0, 09/02, page 15 of 732 2.2.2 Control Registers The control registers consist of three 32-bit registers: status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception processing vector area (including interrupts). Status Register (SR): Bit Bit Name Initial Value R/W Description 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 — — — — — — — — — — — — — — — — — — — — — — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reserved bits. This bit is always read as 0. The write value should always be 0. 9 M Undefined R/W Used by the DIV0U, DIV0S, and DIV1 instructions. 8 Q Undefined R/W Used by the DIV0U, DIV0S, and DIV1 instructions. |
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