SH7145 datasheet(13/773 Pages) RENESAS

13 / 773 page

Rev. 2.0, 09/02, page xi of xxxviii

6.3.1

Interrupt Control Register 1 (ICR1)..................................................................... 70

6.3.2

Interrupt Control Register 2 (ICR2)..................................................................... 72

6.3.3

IRQ Status Register (ISR).................................................................................... 74

6.3.4

Interrupt Priority Registers A to J (IPRA to IPRJ)............................................... 75

6.4

Interrupt Sources ............................................................................................................... 77

6.4.1

External Interrupts ............................................................................................... 77

6.4.2

On-Chip Peripheral Module Interrupts ................................................................ 78

6.4.3

User Break Interrupt ............................................................................................ 78

6.4.4

H-UDI Interrupt ................................................................................................... 78

6.5

Interrupt Exception Processing Vectors Table.................................................................. 79

6.6

Interrupt Operation............................................................................................................ 82

6.6.1

Interrupt Sequence ............................................................................................... 82

6.6.2

Stack after Interrupt Exception Processing .......................................................... 84

6.7

Interrupt Response Time ................................................................................................... 85

6.8

Data Transfer with Interrupt Request Signals ................................................................... 87

6.8.1

Handling Interrupt Request Signals as Sources for DTC Activating

and CPU Interrupt, but Not DMAC Activating.................................................... 88

6.8.2

Handling Interrupt Request Signals as Sources for Activating DMAC,

but Not CPU Interrupt and DTC Activating ........................................................ 88

6.8.3

Handling Interrupt Request Signals as Source for DTC Activating,

but Not CPU Interrupt and DMAC Activating..................................................... 88

6.8.4

Handling Interrupt Request Signals as Source for CPU Interrupt

but Not DMAC and DTC Activating ................................................................... 89

Section 7 User Break Controller (UBC) ........................................................... 91

7.1

Overview........................................................................................................................... 91

7.2

Register Descriptions ........................................................................................................93

7.2.1

User Break Address Register (UBAR)................................................................. 93

7.2.2

User Break Address Mask Register (UBAMR) ................................................... 93

7.2.3

User Break Bus Cycle Register (UBBR) ............................................................. 94

7.2.4

User Break Control Register (UBCR).................................................................. 95

7.3

Operation........................................................................................................................... 96

7.3.1

Flow of the User Break Operation ....................................................................... 96

7.3.2

Break on On-Chip Memory Instruction Fetch Cycle ........................................... 98

7.3.3

Program Counter (PC) Values Saved................................................................... 98

7.4

Examples of Use ............................................................................................................... 99

7.5

Usage Notes ...................................................................................................................... 101

7.5.1

Simultaneous Fetching of Two Instructions......................................................... 101

7.5.2

Instruction Fetches at Branches ........................................................................... 101

7.5.3

Contention between User Break and Exception Processing ................................ 102

7.5.4

Break at Non-Delay Branch Instruction Jump Destination.................................. 102

7.5.5

Module Standby Mode Setting ............................................................................ 102

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