AD5601 datasheet(5/20 Pages) AD

5 / 20 page

Preliminary Technical Data

AD5601/AD5611/AD5621

Rev. PrC | Page 5 of 20

B Version1

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER REQUIREMENTS

VDD

2.7

5.5

All digital inputs at 0 or VDD

IDD (Normal Mode)

DAC active and excluding load current

VDD = ±4.5 V to ±5.5 V

100

µA

VIH = VDD and VIL = GND

VDD = ±2.7 V to ±3.6 V

µA

VIH = VDD and VIL = GND

IDD (All Power-Down Modes)

VDD = ±4.5 V to ±5.5 V

0.2

µA

VIH = VDD and VIL = GND

VDD = ±2.7 V to ±3.6 V

0.05

µA

VIH = VDD and VIL = GND

POWER EFFICIENCY

IOUT/IDD

TBD

ILOAD = 2 mA and VDD = ±5 V

1 Temperature ranges are as follows: B Version: –40°C to +125°C, typical at +25°C.

2 Linearity calculated using a reduced code range.

3 Guaranteed by design and characterization, not production tested.

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.

Table 3.

Parameter

Limit1

Unit

Test Conditions/Comments

t12

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC to SCLK falling edge setup time

ns min

Data setup time

4.5

ns min

Data hold time

ns min

SCLK falling edge to SYNC rising edge

ns min

Minimum SYNC high time

ns min

SYNC rising edge to next SCLK fall ignore

1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2 Maximum SCLK frequency is 30 MHz.

D14

D15

DIN

SYNC

SCLK

D15

D14

Figure 2. Timing Diagram

AD5601 Datasheet(PDF) 5 Page - Analog Devices

AD5601 Datasheet(HTML) 5 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL