AD5601 datasheet(15/20 Pages) AD

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Preliminary Technical Data

AD5601/AD5611/AD5621

Rev. PrC | Page 15 of 20

AD5601/AD5611/AD5621 to 68HC11/68L11 Interface

Figure 30 shows a serial interface between the AD5601/

AD5611/AD5621 and the 68HC11/68L11 microcontrollers.

SCK of the 68HC11/68L11 drives the SCLK of the AD5601/

AD5611/AD5621, while the MOSI output drives the serial data

line of the DAC. The SYNC signal is derived from a port line

(PC7). The setup conditions for correct operation of this

interface are as follows: the 68HC11/68L11 should be

configured so that its CPOL bit is a 0 and its CPHA bit is a 1.

When data is being transmitted to the DAC, the SYNC line is

taken low (PC7). When the 68HC11/68L11 is configured as

above, data appearing on the MOSI output is valid on the falling

edge of SCK. Serial data from the 68HC11/68L11 is transmitted

in 8-bit bytes with only eight falling clock edges occurring in

the transmit cycle. Data is transmitted MSB first. To load data to

the AD5601/AD5611/AD5621, PC7 is left low after the first

eight bits are transferred, and a second serial write operation is

performed to the DAC. PC7 is taken high at the end of this

procedure.

68HC11/

68L11

AD5601/AD5611/

AD5621*

*ADDITIONAL PINS OMITTED FOR CLAIRTY

PC7

SCK

MOSI

SYNC

SCLK

DIN

Figure 30. AD5601/AD5611/AD5621 to 68HC11/68L11 Interface

AD5601/AD5611/AD5621 to Blackfin® ADSP-BF53X

Interface

Figure 31 shows a serial interface between the AD5601/

AD5611/AD5621 and the Blackfin ADSP-BF53x

microprocessors. The ADSP-BF53x processor family

incorporates two dual-channel synchronous serial ports,

SPORT1 and SPORT0, for serial and multiprocessor

communications. Using SPORT0 to connect to the AD5601/

AD5611/AD5621, the setup for the interface is as follows:

DT0PRI drives the SDIN pin of the AD5601/AD5611/AD5621,

while TSCLK0 drives the SCLK of the part. The SYNC is driven

from TFS0.

ADSP-BF53X

AD5601/AD5611/

AD5621

*ADDITIONAL PINS OMITTED FOR CLAIRTY

DT0PRI

TSCLK0

TFS0

DIN

SCLK

SYNC

Figure 31. AD5601/AD5611/AD5621 to Blackfin ADSP-BF53X Interface

AD5601/AD5611/AD5621 to 80C51/80L51 Interface

Figure 32 shows a serial interface between the AD5601/

AD5611/AD5621 and the 80C51/80L51 microcontroller. The

setup for the interface is as follows: TXD of the 80C51/80L51

drives SCLK of the AD5601/AD5611/AD5621, while RXD

drives the serial data line of the part. The SYNC signal is again

derived from a bit programmable pin on the port. In this case,

port line P3.3 is used. When data is to be transmitted to the

AD5601/AD5611/AD5621, P3.3 is taken low. The 80C51/80L51

transmit data only in 8-bit bytes; thus, only eight falling clock

edges occur in the transmit cycle. To load data to the DAC, P3.3

is left low after the first eight bits are transmitted, and a second

write cycle is initiated to transmit the second byte of data. P3.3

is taken high following the completion of this cycle. The 80C51/

80L51 output the serial data in a format that has the LSB first.

The AD5601/AD5611/AD5621 require their data with the MSB

as the first bit received. The 80C51/80L51 transmit routine

should take this into account.

80C51/80L51*

AD5601/AD5611/

AD5621*

*ADDITIONAL PINS OMITTED FOR CLAIRTY

P3.3

TXD

RXD

SYNC

SCLK

DIN

Figure 32. AD5601/AD5611/AD5621 to 80C51/80L51 Interface

AD5601/AD5611/AD5621 to MICROWIRE Interface

Figure 33 shows an interface between the AD5601/AD5611/

AD5621 and any MICROWIRE compatible device. Serial data is

shifted out on the falling edge of the serial clock and is clocked

into the AD5601/AD5611/AD5621 on the rising edge of the SK.

MICROWIRE*

AD5601/AD5611/

AD5621*

*ADDITIONAL PINS OMITTED FOR CLAIRTY

SYNC

SCLK

DIN

Figure 33. AD5601/AD5611/AD5621 to MICROWIRE Interface

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