MAX5166LECM datasheet(7/12 Pages) MAXIM

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Hold Step

When switching between sample mode and hold

mode, the voltage of the hold capacitor changes due to

charge injection from stray capacitance. This voltage

change, called hold step, is minimized by limiting the

amount of stray capacitance seen by the hold capaci-

tor. The MAX5166 limits the hold step to 0.25mV (typ).

An output capacitor to ground can be used to filter out

this small hold-step error.

Output

The MAX5166 contains an output buffer for each multi-

plexer channel (32 total), so the hold capacitor sees a

high-impedance input, reducing the droop rate. While

in hold mode, the hold capacitor discharges at a rate of

1mV/sec (typ). The buffer also provides a low output

impedance; however, the device contains output resis-

tors in series with the buffer output (Figure 1) for select-

ed output filtering. To provide greater design flexibility,

the MAX5166 is available with an RO of 50

Ω, 500Ω, or

Ω.

Note: Output loads increase the analog supply cur-

rent (IDD and ISS). Excessive loading of the output(s)

damages the device by consuming more power than

the device will dissipate (see Absolute Maximum

Ratings). The resistor-divider formed by the output

resistor (ROUT_) and load impedance (RL) scales the

sampled voltage (VSAMP). Determine the output volt-

age (VOUT_) as follows:

Voltage Gain = AV = RL/(RL + ROUT)

VOUT_ = VSAMP · AV

The maximum output voltage range depends on the

analog supply voltages available and the scaling factor

used:

(VSS + 0.75V) · AV

≤ VOUT_ ≤ (VDD - 2.4V) · AV

when RL =

∞, then AV = 1, and this equation becomes

(VSS + 0.75V)

≤ VOUT ≤ (VDD - 2.4V).

Timing Definitions

Acquisition time (tAQ) is the amount of time the

MAX5166 must remain in sample mode for the hold

capacitor to acquire an accurate sample. The hold-

mode settling time (tH) is the amount of time necessary

for the output voltage to settle to its final value.

Aperture delay (tAP) is the time interval required to dis-

connect the input from the hold capacitor. The inhibit

pulse width (tPW) is the amount of time the MAX5166

must remain in hold mode while the address is

changed. The data setup time (tDS) is the amount of

time an address must be maintained before the

address becomes valid. The data hold time (tDH) is the

amount of time an address must be maintained after

mode select has gone from low to high (Figure 2).

32-Channel Sample/Hold Amplifier

with Four Multiplexed Inputs

_______________________________________________________________________________________

Table 1. Output Selection

Table 2. Mode Selection

ADDRESS

OUT2

OUT3

OUT6

OUT0

OUT7

OUT1

OUT4

OUT5

OUT10

OUT11

OUT14

OUT8

OUT15

OUT9

OUT12

OUT13

OUT18

OUT19

OUT22

OUT16

OUT23

OUT17

OUT20

OUT21

OUTPUT SELECTED

OUT26

OUT27

OUT30

OUT24

OUT31

OUT25

OUT28

OUT29

MUX0

MUX1

MUX2

MUX3

0 = Logic Low, 1 = Logic High

Sample mode enabled on selected

analog multiplexer and channel

(Table 1).

Hold mode enabled on selected

analog multiplexer and channel

(Table 1).

MODE-SELECT

INPUTS* (M3–M0)

ACTION

0 = Logic Low, 1 = Logic High

* Only one M_ input asserted low; all others must be logic high

to meet the timing specification (see Single vs. Simultaneous

Sampling).

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