Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

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13

AGC Dwell-Time Settings

The AGC dwell timer holds the AGC in low-gain state

for a set amount of time after the power level drops

below the AGC switching threshold. After that set

amount of time, if the power level is still below the AGC

threshold, the LNA goes into high-gain state. This is

important for ASK since the modulated data may have

a high level above the threshold and low level below

the threshold, which without the dwell timer would

cause the AGC to switch on every bit.

The MAX7030 uses the three AGC control pins (AGC0,

AGC1, AGC2) to set seven user-controlled, dwell-timer

settings. The AGC dwell time is dependent on the crys-

tal frequency and the bit settings of the AGC control

pins. To calculate the dwell time, use the following

equation:

where K is an odd integer in decimal from 11 to 23, deter-

To calculate the value of K, use the following equation

and use the next integer higher than the calculated

result:

K

For Manchester Code (50% duty cycle), set the dwell

time to at least twice the bit period. For nonreturn-to-

zero (NRZ) data, set the dwell to greater than the peri-

od of the longest string of zeros or ones. For example,

12.679MHz) with a data rate of 2kbps (bit period =

250µs), the dwell time needs to be greater than 500µs:

K

Choose the AGC pin settings for K to be the next odd-

integer value higher than 12.546, which is 13. This says

that AGC1 is set high and AGC0 and AGC2 are set low.

Mixer

A unique feature of the MAX7030 is the integrated

image rejection of the mixer. This eliminates the need

for a costly front-end SAW filter for many applications.

The advantage of not using a SAW filter is increased

sensitivity, simplified antenna matching, less board

space, and lower cost.

The mixer cell is a pair of double-balanced mixers that

perform an IQ downconversion of the RF input to the

10.7MHz intermediate frequency (IF) with low-side

then combines these signals to achieve a typical 46dB

of image rejection over the full temperature range. Low-

side injection is required as high-side injection is not

possible due to the on-chip image rejection. The IF out-

put is driven by a source follower, biased to create a

driving impedance of 330

Ω to interface with an off-chip

330

Ω ceramic IF filter. The voltage-conversion gain dri-

ving a 330

Ω load is approximately 20dB. Note that the

MIXIN+ and MIXIN- inputs are functionally identical.

Integer-N Phase-Locked Loop (PLL)

The MAX7030 utilizes a fixed-integer-N PLL to generate

the receive LO. All PLL components, including the loop

filter, voltage-controlled oscillator, charge pump, asyn-

chronous 24x divider, and phase-frequency detector

are integrated internally. The loop bandwidth is approx-

imately 500kHz. The relationship between RF, IF, and

reference frequencies is given by:

Dwell Time

f

K

XTAL

=

2

AGC2

AGC1

AGC0

DESCRIPTION

00

0

AGC disabled, high gain selected

00

1

K = 11

01

0

K = 13

01

1

K = 15

10

0

K = 17

10

1

K = 19

11

0

K = 21

11

1

K = 23

MAX7030