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TPA3138D2

SLOS993A – MARCH 2018 – REVISED JUNE 2018

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(1)

Set SD/FAULT to high level, make sure the pull-up resistor is larger than 4.7 k

Ω and smaller than 500 kΩ

(2)

Set GAIN_SEL and MODE_SEL to low level, make sure pull down resistor<10k

Ω

(3)

The TPA3138D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected

to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection

shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Supply voltage

PVCC, AVCC

3.5

14.4

V

High-level input voltage

2

AVCC

V

Low-level input voltage

0.8

V

Low-level output voltage

0.8

V

High-level input current

50

µA

Low-level input current

V

5

µA

–10

85

°C

-10

150

°C

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.4 Thermal Information

TPA3138D2

UNIT

PWP (HTSSOP)

28 PINS

Junction-to-ambient thermal resistance

30.3

°C/W

Junction-to-case (top) thermal resistance

33.5

°C/W

Junction-to-board thermal resistance

17.5

°C/W

Junction-to-top characterization parameter

0.9

°C/W

Junction-to-board characterization parameter

7.2

°C/W

Junction-to-case (bottom) thermal resistance

0.9

°C/W