XRT8020

650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS

REV. 1.0.2

I

DESCRIPTION .................................................................................................................... 1

APPLICATIONS ......................................................................................................................................... 1

FEATURES ................................................................................................................................................ 1

Figure 1. Block Diagram of the XRT8020 ........................................................................................ 1

ORDERING INFORMATION ............................................................................................................... 2

Figure 2. XRT8020 Pin Location - (Top View) ................................................................................. 2

ABSOLUTE MAXIMUM RATINGS

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ELECTRICAL CHARACTERISTICS

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Figure 3. LVDS Output Waveforms and Test Circuits .................................................................... 5

1.0 Calibration ................................................................................................................................................. 5

TABLE 1: FREQUENCY SELECTION TABLE .............................................................................................. 5

TABLE 2: POWER-DOWN AND OUTPUT TRI-STATE SELECTION TABLE ....................................................... 5

2.0 Crystal selection ....................................................................................................................................... 6

3.0 data and plots ........................................................................................................................................... 6

Figure 4. Input Referenced Jitter Connection Diagram ................................................................. 6

Figure 5. Simplified Block Diagram of the XRT8020 and PECL Receiver .................................... 7

Figure 6. LVDS Differential Output ..................................................................................................7

Figure 7. PECL Differential Output ..................................................................................................8

Figure 8. PECL Single-Ended Outputs (Positive and Negative Output Referenced to Ground) 9

ORDERING INFORMATION ............................................................................................. 10

REVISIONS ................................................................................................................................................. 11