ADAU1361BCPZ-R7 datasheet(58/80 Pages) AD

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ADAU1361

Data Sheet

Rev. D | Page 58 of 80

R16: Serial Port Control 1, 16,406 (0x4016)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BPF[2:0]

ADTDM

DATDM

MSBP

LRDEL[1:0]

Table 43. Serial Port Control 1 Register

Bits

Bit Name

Description

[7:5]

BPF[2:0]

Number of bit clock cycles per LRCLK audio frame.

Setting

Bit Clock Cycles

000

64 (default)

001

010

011

128

100

Reserved

101

Reserved

110

Reserved

111

Reserved

ADTDM

ADC serial audio data channel position in TDM mode.

0 = left first (default).

1 = right first.

DATDM

DAC serial audio data channel position in TDM mode.

0 = left first (default).

1 = right first.

MSBP

MSB position in the LRCLK frame.

0 = MSB first (default).

1 = LSB first.

[1:0]

LRDEL[1:0]

Data delay from LRCLK edge (in BCLK units).

Setting

Delay (Bit Clock Cycles)

1 (default)

ADAU1361BCPZ-R7 Datasheet(PDF) 58 Page - Analog Devices

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