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IRISMPS3

through R11/D6 to the FB pin of the IRIS4013K.

If the bias winding voltage is below the threshold Q1 is off and no quasi-resonant signal is passed, this causes

U1 to operate in the PRC mode with a fixed of time of 50us, this results in a further lowering of the Vcc voltage to

provide some hysteresis to prevent spurious changing between modes.

Circuit Waveforms

The following plots show waveforms taken from the circuit under various stated conditions

Fig 2) Drain (D) voltage of IRIS4013K (CH1) and FB voltage (CH3) 90VAC in Full load

Fig 2) shows the drain voltage of the IRIS4013K and the FB voltage with full load output at 90VAC input.

Note that point X marked on the drain waveform shows the detection point for the quasi-resonant signal which

is the lowest point on the drain waveform after the energy is transferred.

Fig 3) shows the drain voltage and the feedback pin (FB) voltage at 265VAC input again with a full load

output. Note that at the start of the ON time for the FET the FB pin signal has a higher dv/dt rise. This is due to

the feedback signal from the output creating the offset voltage to keep the output power constant. Also note that

the on-time is shorter and hence the operating frequency is higher.