FUSB301A datasheet(7/14 Pages) ONSEMI

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FUSB301A

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FAST MODE I2C SPECIFICATIONS (Note 3)(see Figure 4) (continued)

Symbol

Unit

Fast Mode

Parameter

Symbol

Unit

Max.

Min.

Parameter

tSU;STO

Set−up Time for STOP Condition

0.6

tBUF

BUS−Free Time between STOP and START Conditions

1.3

tSP

Pulse Width of Spikes that Must Be Suppressed by the Input

Filter

3. Guaranteed by characterization. Not production tested.

4. A fast−mode I2C bus device can be used in a standard−mode I2C bus system, but the requirement tSU;DAT ≥ 250 ns must be met. This is

automatically the case of the device does not stretch the LOW period of the I2C_SCL signal. If such a device does stretch the LOW period

I2C_SCL signal, it must output the next data bit to the I2C_SDA line tr_max + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard−mode

I2C bus specification) before the I2C_SCL line is released.

5. Cb equals the total capacitance of one bus line in pF. If mixed with high−speed devices, faster fall times are allowed according to the I2C

specification.

Figure 4. Definition of Timing for Full−Speed Mode Devices on the I2C Bus

I2C INTERFACE

The FUSB301A includes a full I2C slave controller. The

I2C slave fully complies with the I2C specification version 6

requirements. This block is designed for fast mode.

Examples of an I2C write and read sequence are shown

Figure 5 and Figure 6 respectively.

Figure 5. I2C Write Example

NOTE: Single Byte read is initiated by Master with P immediately following first data byte.

Figure 6. I2C Read Example

NOTE: If Register is not specified Master will begin read from current register. In this case only sequence showing in Red bracket

is needed.

Single or multi byte read executed from current register location (Single Byte read

is initiated by Master with NA immediately following first data byte)

I2C ADDRESS

The I2CADDR bit high or low is indicated in bit3 of the

slave address shown in Table 2.

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