ADV7280 datasheet(13/28 Pages) AD

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Data Sheet

ADV7280

Rev. A | Page 13 of 28

THEORY OF OPERATION

The ADV7280/ADV7280-M are versatile one-chip, multiformat

video decoders. The ADV7280/ADV7280-M automatically detect

standard analog baseband video signals compatible with world-

wide NTSC, PAL, and SECAM standards in the form of composite,

S-Video, and component video.

The ADV7280 converts the analog video signals into an 8-bit

YCrCb 4:2:2 component video data stream that is compatible

with the ITU-R BT.656 interface standard.

The ADV7280-M converts the analog video signals into an 8-bit

YCrCb 4:2:2 video data stream that is output over a MIPI CSI-2

interface. The MIPI CSI-2 output interface connects to a wide

range of video processors and FPGAs.

The ADV7280/ADV7280-M accept composite video signals,

as well as S-Video and YPbPr video signals, supporting a wide

range of consumer and automotive video sources. The accurate

10-bit analog-to-digital conversion provides professional quality

video performance for consumer applications with true 8-bit

data resolution.

The advanced interlaced-to-progressive (I2P) function allows the

ADV7280/ADV7280-M to convert an interlaced video input into

a progressive video output. This function is performed without the

need for external memory. The ADV7280/ADV7280-M use edge

adaptive technology to minimize video defects on low angle lines.

The automatic gain control (AGC) and clamp restore circuitry

allows an input video signal peak-to-peak range of 0 V to 1.0 V

at the analog video input pins of the ADV7280/ADV7280-M.

Alternatively, the AGC and clamp restore circuitry can be bypassed

for manual settings.

The ADV7280/ADV7280-M support a number of other func-

tions, including 8-bit to 6-bit down dither mode and adaptive

contrast enhancement (ACE).

The ADV7280/ADV7280-M are programmed via a 2-wire,

serial bidirectional port (I2C compatible) and are fabricated in

a 1.8 V CMOS process. The monolithic CMOS construction

of the ADV7280/ADV7280-M ensures greater functionality with

lower power dissipation. The LFCSP package option makes these

decoders ideal for space-constrained portable applications.

ANALOG FRONT END (AFE)

The analog front end (AFE) of the ADV7280/ADV7280-M

comprises a single high speed, 10-bit ADC that digitizes the

analog video signal before applying it to the standard definition

processor (SDP).

The AFE also includes an input mux that enables multiple video

signals to be applied to the ADV7280/ADV7280-M. The input

mux allows up to four composite video signals to be applied to

the ADV7280 and up to eight composite video signals to be applied

to the ADV7280-M.

Current clamps are positioned in front of the ADC to ensure

that the video signal remains within the range of the converter.

A resistor divider network is required before each analog input

channel to ensure that the input signal is kept within the range of

the ADC (see the Input Network section). Fine clamping of the

video signal is performed downstream by digital fine clamping

within the ADV7280/ADV7280-M.

Table 11 lists the three ADC clock rates that are determined by

the video input format to be processed. These clock rates ensure

4× oversampling per channel for CVBS, Y/C, and YPrPb modes.

Table 11. ADC Clock Rates

Input Format

ADC Clock Rate (MHz)1

Oversampling

Rate per Channel

CVBS

57.27

4×

Y/C (S-Video)

114

4×

YPrPb

172

4×

Based on a 28.63636 MHz crystal between the XTALP and XTALN pins.

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