ADV7280 datasheet(21/28 Pages) AD

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Data Sheet

ADV7280

Rev. A | Page 21 of 28

ITU-R BT.656 Tx CONFIGURATION (ADV7280 ONLY)

The ADV7280 receives analog video and outputs digital video

according to the ITU-R BT.656 specification. The ADV7280

outputs the ITU-R BT.656 video data stream over the P0 to P7

data pins and has a line-locked clock (LLC) pin and two synchro-

nization pins (HS and VS/FIELD/SFL).

Video data is output over the P0 to P7 pins in YCrCb 4:2:2 format.

Synchronization signals are automatically embedded in the video

data signal in accordance with the ITU-R BT.656 specification.

The LLC output is used to clock the output data on the P0 to P7

pins at a nominal frequency of 27 MHz.

The two synchronization pins (HS and VS/FIELD/SFL) output a

variety of synchronization signals such as horizontal sync, vertical

sync, field sync, and color subcarrier frequency lock (SFL) sync.

The majority of these synchronization signals are already embed-

ded in the video data. Therefore, the use of the synchronization

pins is optional.

(OPTIONAL)

VS/FIELD/SFL

(OPTIONAL)

ITU-R BT.656

DATA

STREAM

VIDEO

DECODER

ANALOG

VIDEO

INPUT

LLC

ADV7280

STANDARD

DEFINITION

PROCESSOR

ANALOG

FRONT

END

Figure 11. ITU-R BT.656 Output Stage of the ADV7280

ADV7280 Datasheet(PDF) 21 Page - Analog Devices