AD9528 datasheet(37/67 Pages) AD

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Data Sheet

AD9528

Rev. D | Page 37 of 67

SCLK

SDIO

SDO

16-BIT INSTRUCTION HEADER

A12

A13

A14

R/W

A11 A10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

DON'T CARE

DON'T

CARE

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 41. Serial Control Port Read—MSB First, Address Decrement, Four Bytes of Data

DON'T CARE

A14

A13

A12

A11

A10

DON'T CARE

R/W

tDS

tDH

tHIGH

tLOW

tCLK

SCLK

SDIO

Figure 42. Timing Diagram for Serial Control Port Write—MSB First

DATA BIT N – 1

DATA BIT N

SCLK

SDIO

SDO

tDV

Figure 43. Timing Diagram for Serial Control Port Register Read—MSB First

SCLK DON'T CARE

DON'T CARE

16-BIT INSTRUCTION HEADER

SDIO

DON'T CARE

A0 A1 A2 A3

A5 A6 A7

A9 A10 A11 A12

R/W

A14

A13

D2 D3 D4

D5 D6

D1 D2

D3 D4 D5

Figure 44. Serial Control Port Write—LSB First, Address Increment, Two Bytes of Data

SCLK

SDIO

tHIGH

tLOW

tCLK

tDS

tDH

BIT N

BIT N + 1

Figure 45. Serial Control Port Timing—Write

Table 27. Serial Control Port Timing

Parameter

Description

tDS

Setup time between data and the rising edge of SCLK

tDH

Hold time between data and the rising edge of SCLK

tCLK

Period of the clock

Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle)

Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle)

tHIGH

Minimum period that SCLK is in a logic high state

tLOW

Minimum period that SCLK is in a logic low state

tDV

SCLK to valid SDIO (see Figure 43)

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