AD9548BCPZ datasheet(59/111 Pages) AD

59 / 111 page

Data Sheet

AD9548

Rev. G | Page 59 of 111

INPUT/OUTPUT PROGRAMMING REGISTERS

The register map spans an address range from 0x0000 through

0x0E3F (0 to 3647, decimal). Each address provides access to one

byte (eight bits) of data. Each individual register is identified by its

four-digit hexadecimal address (for example, Register 0x0A10). In

some cases, a group of addresses collectively defines a register

(for example, the IRQ mask register consists of Register 0x0209,

In general, when a group of registers defines a control parameter,

the LSB of the value resides in the D0 position of the register with

the lowest address. The bit weight increases right to left, from the

lowest register address to the highest register address. For example,

the default value of the incremental phase lock offset step size

hexadecimal number, 0x03E8 (not 0xE803).

Note that the EEPROM storage sequence registers (Address 0x0E10

to Address 0x0E3F) are an exception to the above convention (see

the EEPROM Instructions section).

BUFFERED/ACTIVE REGISTERS

There are two broad categories of registers in the AD9548—

buffered and active (see Figure 68). Buffered registers need an

input/output update to apply their contents to the internal device

functions. In contrast, active registers do not require an

input/output update to transfer data between the buffer registers

and the internal device functions. In operation, the user programs

as many buffer registers as desired and then issues an input/output

update. The input/output update occurs by writing to Register

0x0005, Bit 0 = 1 (or by the external application of the necessary

logic level to one of the multifunction pins previously programmed

as an input/output update input). The contents of buffer registers

connected directly to the internal device functions affect those

functions immediately. The contents of buffer registers that connect

to active registers do not affect the internal device functions until

the input/output update event occurs.

An L in the Opt column of the register map indicates an active

(or live) register. An S or a C in the Opt column of the register

map identifies a buffered register. An S entry means that the

input/output update signal to the active register is synchronized

with the serial port clock or with an input signal driving one of

the multifunction pins. On the other hand, a C entry means

that the input/output update signal to the active register is

synchronized with a clock signal derived from the internal

system clock (fS/32), as shown in Figure 68.

When reading back a register that has both buffered and active

contents, the user can use Register 0x0004, Bit 0 to select

whether to read back the buffer or active contents. Readback of

the active contents occurs when Register 0x0004, Bit 0 = 0, and

readback of the buffer contents occurs when Register 0x0004,

Bit 0= 1. Note that a read-only active register requires an

input/output update before reading its contents.

FROM

MULTIFUNCTION

PIN LOGIC

SERIAL

CONTROL

PORT

fS/32

EDGE

DETECT

CS/SDA

SCLK/SCL

SDIO

SDO

Figure 68. Buffered and Active Registers

AUTOCLEAR REGISTERS

An A in the Opt column of the register map identifies an autoclear

effect following an input/output update. The bit is cleared by the

internal device logic upon completion of the prescribed action.

Read and write access to the register map may be restricted based

on the register in question, the source and direction of access, and

the current state of the device. Each register can be classified as one

or more access types. When more than one type applies, the most

restrictive condition that applies at the moment is used.

Whenever access is denied to a register, all attempts to read the

ignored. Access to nonexistent registers is handled in the same way

as for a denied register.

Regular Access

Registers with regular access do not fall into any other category.

Both read and write access to registers of this type can be from

either the serial ports or EEPROM controller. Only one of these

sources can have access to a register at any given time (access is

mutually exclusive). When the EEPROM controller is active, either

in load or store mode, it has exclusive access to these registers.

Read-Only Access

An R in the Opt column of the register map identifies read-only

registers. Access is available at all times, including when the

EEPROM controller is active.

Exclusion from EEPROM Access

An E in the Opt column of the register map identifies a register

with contents that are inaccessible to the EEPROM. The contents of

this type of register cannot be transferred directly to the

EEPROM or vice versa. Note that read-only registers (R) are

inaccessible to the EEPROM, as well.

AD9548BCPZ Datasheet(PDF) 59 Page - Analog Devices

AD9548BCPZ Datasheet(HTML) 59 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL