AD1839AAS datasheet(13/24 Pages) AD

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AD1839A

Rev. B | Page 13 of 24

To maintain the highest performance possible, the clock

jitter of the master clock signal should be limited to less than

300 ps rms, measured using the edge-to-edge technique. Even at

these levels, extra noise or tones may appear in the DAC outputs

if the jitter spectrum contains large spectral peaks. It is highly

recommended that the master clock be generated by an inde-

pendent crystal oscillator. In addition, it is especially important

that the clock signal not be passed through an FPGA or other

large digital chip before being applied to the AD1839A. In most

cases, this induces clock jitter because the clock signal is sharing

common power and ground connections with unrelated digital

output signals.

RESET AND POWER-DOWN

PD/RST powers down the chip and sets the control registers

to their default settings. After PD/RST is deasserted, an initial-

ization routine runs inside the device to clear all memories to

zero. The initialization lasts approximately 20 LRCLK intervals.

During this time, it is recommended that no SPI writes occur.

POWER SUPPLY AND VOLTAGE REFERENCE

The AD1839A is designed for 5 V supplies. Separate power

supply pins are provided for the analog and digital sections.

These pins should be bypassed with 100 nF ceramic chip

capacitors, as close to the pins as possible, to minimize noise

pickup. A bulk aluminum electrolytic capacitor of at least 22 µF

should also be provided on the same PC board as the codec. For

critical applications, improved performance is obtained with

separate supplies for the analog and digital sections. If this is

not possible, it is recommended that the analog and digital

supplies be isolated by two ferrite beads in series with the

bypass capacitor of each supply. It is important that the analog

supply be as clean as possible.

The internal voltage reference is brought out on the FILTR pin

and should be bypassed as close as possible to the chip, with a

parallel combination of 10 µF and 100 nF. The reference voltage

may be used to bias external op amps to the common-mode

voltage of the analog input and output signal pins. The current

drawn from the VREF pin should be limited to less than 50 µA.

SERIAL CONTROL PORT

The AD1839A has an SPI compatible control port to permit

programming the internal control registers for the ADCs and

DACs, and for reading the ADC signal levels from the internal

peak detectors. The SPI port is a 4-wire serial control port. The

format is similar to the Motorola SPI format except the input

data-word is 16 bits wide. The maximum serial bit clock

frequency is 12.5 MHz and may be completely asynchronous to

the sample rate of the ADCs and DACs. Figure 15 shows the

format of the SPI signal.

CLOCK SCALING

×1

×2

×2/3

MCLK

12.288MHz

DAC INPUT

ADC OUTPUT

DAC ENGINE

INTERPOLATION

FILTER

Σ-∆

MODULATOR

DAC

48kHz/96kHz/192kHz

48kHz/96kHz

ANALOG

OUTPUT

ANALOG

INPUT

IMCLK = 24.576MHz

ADC ENGINE

OPTIONAL

HPF

DECIMATOR/

FILTER

Σ-∆

MODULATOR

Figure 14. Modular Clocking Scheme

CLATCH

CCLK

CIN

COUT

D15

D14

tCCH tCCL

tCDS tCDH

tCLS

tCLH

tCOD

tCOTS

tCCP

tCOE

Figure 15. Format of SPI Timing

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