AD1839AAS datasheet(22/24 Pages) AD

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AD1839A

Rev. B | Page 22 of 24

Table 16. ADC Control 2

Function

ADC MUTE

Address

R/W

RES

Master/Slave Aux Mode

ADC Data Format

ADC Data-

Word Width

AUXDATA

RES

Right

Left

15, 14, 13, 12

8, 7, 6

5, 4

1101

0 = Slave

000 = I2S

00 = 24 Bits

0 = Off

0 = On

1 = Master

001 = RJ

01 = 20 Bits

1 = On

1 = Mute

010 = DSP

10 = 16 Bits

011 = LJ

11 = Reserved

100 = Packed 256

101 = Packed 128

110 = Auxiliary 256

111 = Auxiliary 512

Table 17. ADC Control 3

Function

Address

R/W RES

RES

Reserved

IMCLK Clocking Scaling

ADC Peak Readback

DAC Test Mode

ADC Test Mode

15, 14,

13, 12

9, 8

7, 6

4, 3, 2

1, 0

1110

0, 0

00 = MCLK × 2

0 = Disabled Peak Readback

000 = Normal Mode

00 = Normal Mode

01 = MCLK

1 = Enabled Peak Readback

All Others Reserved

10 = MCLK × 2/3

11 = MCLK × 2

CASCADE MODE

Dual AD1839A Cascade

The AD1839A can be cascaded to an additional AD1839A that,

in addition to six external stereo ADCs and two external stereo

DACs, can be used to create a 32-channel audio system with

16 inputs and 16 outputs. The cascade is designed to connect

to a SHARC DSP and operates in a time division multiplexing

(TDM) format. Figure 28 shows the connection diagram for

cascade operation. The digital interface for both parts must be

set to operate in Auxiliary 512 mode by programming ADC

Control Register 2. AD1839A Device 1 is set as the master

device by connecting the M/S pin to DGND; AD1839A

Device 2 is set as a slave device by connecting the M/S to

ODVDD. Both devices should be run from the same MCLK

and PD/RST signals to ensure that they are synchronized. With

Device 1 set as a master, it generates the frame-sync and bit

clock signals. These signals are sent to the SHARC and Device 2,

ensuring that both know when to send and receive data.

The cascade can be thought of as two 256-bit shift registers, one

for each device. At the beginning of a sample interval, the shift

registers contain the ADC results from the previous sample

interval. The first shift register (Device 1) clocks data into the

SHARC and clocks in data from the second shift register

(Device 2). While this is happening, the SHARC is sending DAC

data to the second shift register. By the end of the sample

interval, all 512 bits of ADC data in the shift registers have been

clocked into the SHARC and replaced by DAC data, which is

subsequently written to the DACs. Figure 29 shows the timing

diagram for the cascade operation.

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