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ICS557-03 Datasheet(PDF) 7 Page - Integrated Circuit Systems |
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ICS557-03 Datasheet(HTML) 7 Page - Integrated Circuit Systems |
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7 / 9 page ![]() PCI-EXPRESS CLOCK SOURCE MDS 557-03 E 7 Revision 061005 In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com ICS557-03 AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1 Unless stated otherwise, VDD=3.3 V ±10%, Ambient Temperature -40 to +85 °C Note 1: Test setup is RL=50 ohms with 2 pF, Rr = 475Ω (1%). Note 2: Measurement taken from a single-ended waveform. Note 3: Measurement taken from a differential waveform. Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal. Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high. Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 25 MHz Output Frequency 25 200 MHz Output High Voltage1,2 VOH Notes 1, 2 660 700 850 mV Output Low Voltage1,2 VOL Notes 1, 2 -150 0 mV Crossing Point Voltage1,2 Absolute, Notes 1, 2 250 350 550 mV Crossing Point Voltage1,2,4 Variation over all edges, Notes 1, 2, 4 140 mV Jitter, Cycle-to-Cycle1,3 Notes 1, 3 60 ps Modulation Frequency Spread spectrum 30 31.5 33 kHz Rise Time1,2 tOR From 0.175 V to 0.525 V, Notes 1, 2 175 332 700 ps Fall Time1,2 tOF From 0.525 V to 0.175 V, Notes 1, 2 175 344 700 ps Rise/Fall Time Variation1,2 Notes 1, 2 125 ps Skew between outputs At VDD/2 50 ps Duty Cycle1,3 Notes 1, 3 45 55 % Output Enable Time5 All outputs, Note 5 10 us Output Disable Time5 All outputs, Note 5 10 us Stabilization Time tSTABLE From power-up VDD=3.3 V 3.0 ms Spread Change Time tSPREAD Settling period after spread change 3.0 ms |
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