PRELIMINARY

24

PRELIMINARY

Rev F

CPC5750

Figure 8 and Figure 9 show the timing relationships between the GCI bus signals used to transmit and receive PCM

data and register data when in the GCI Mode. The single-clock or double-clock mode is detected automatically by the

CPC5750 in GCI Mode.

Table 5:

GCI Interface AC Timing

Figure 8: GCI Interface AC Timing with 1x PCLK

Parameter

Test Condition

Symbol

Min

Typ

Max

Units

FS Period

-

-125

-

s

FS Jitter

-

-

-

±120

ns

PCLK Cycle Time - Single-Clocking Mode

-

-488

-

PCLK Cycle Time - Double-Clocking Mode

-

-244

-

PCLK Jitter

-

--

±2

PCLK Rise Time

20% to 80%

--

25

PCLK Fall Time

20% to 80%

--

25

TX Data Access Valid from PCLK Rising

-

--

20

TXZ = 0

--

20

TXZ = 1

--

20

FS Setup Time to PCLK Falling

-

25

-

-

FS Hold Time from PCLK Falling

-

20

-

-

-

25

-

-

-

20

-

-

PCLK

FS

D

RX

D

TX

t

FHD

t

FSU

t

PC

t

RXSU

t

RXSU

t

TXDA

t

RXHD

t

TRIF

t

TRIR

t

FP