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AD9833 Datasheet(PDF) 4 Page - Analog Devices |
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AD9833 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 21 page ![]() AD9833 Data Sheet Rev. F | Page 4 of 21 TIMING CHARACTERISTICS VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.1 Table 2. Parameter Limit at TMIN to TMAX Unit Description t1 40 ns min MCLK period t2 16 ns min MCLK high duration t3 16 ns min MCLK low duration t4 25 ns min SCLK period t5 10 ns min SCLK high duration t6 10 ns min SCLK low duration t7 5 ns min FSYNC to SCLK falling edge setup time t8 min 10 ns min FSYNC to SCLK hold time t8 max t4 − 5 ns max t9 5 ns min Data setup time t10 3 ns min Data hold time t11 5 ns min SCLK high to FSYNC falling edge setup time 1 Guaranteed by design, not production tested. Timing Diagrams t2 t1 MCLK t3 Figure 3. Master Clock t5 t4 t6 t7 t8 t10 t9 4 1 D 5 1 D D0 D1 D2 D14 SCLK FSYNC SDATA D15 t11 Figure 4. Serial Timing |
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