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Data Sheet

AD9833

Rev. F | Page 15 of 21

FREQUENCY AND PHASE REGISTERS

The AD9833 contains two frequency registers and two phase

registers, which are described in Table 7.

Table 7. Frequency and Phase Registers

Size

Description

FREQ0

28 bits

Frequency Register 0. When the FSELECT

bit = 0, this register defines the output

frequency as a fraction of the MCLK

frequency.

FREQ1

28 bits

Frequency Register 1. When the FSELECT

bit = 1, this register defines the output

frequency as a fraction of the MCLK

frequency.

PHASE0

12 bits

Phase Offset Register 0. When the PSELECT

bit = 0, the contents of this register are

added to the output of the phase

accumulator.

PHASE1

12 bits

Phase Offset Register 1. When the PSELECT

bit = 1, the contents of this register are

added to the output of the phase

accumulator.

The analog output from the AD9833 is

fMCLK/228 × FREQREG

where FREQREG is the value loaded into the selected frequency

2π/4096 × PHASEREG

where PHASEREG is the value contained in the selected phase

selected output frequency and the reference clock frequency to

avoid unwanted output anomalies.

The flowchart in Figure 28 shows the routine for writing to the

frequency and phase registers of the AD9833.

Writing to a Frequency Register

When writing to a frequency register, Bit D15 and Bit D14 give

the address of the frequency register.

Table 8. Frequency Register Bits

D15

D14

D13

MSB 14 FREQ0 REG bits

LSB

MSB 14 FREQ1 REG bits

LSB

If the user wants to change the entire contents of a frequency

performed because the frequency registers are 28 bits wide. The

first write contains the 14 LSBs, and the second write contains

the 14 MSBs. For this mode of operation, the B28 (D13) control

bit should be set to 1. An example of a 28-bit write is shown in

Table 9.

Table 9. Writing 0xFFFC000 to the FREQ0 Register

SDATA Input

Result of Input Word

0010 0000 0000 0000

Control word write

(D15, D14 = 00), B28 (D13) = 1,

HLB (D12) = X

0100 0000 0000 0000

FREQ0 register write

(D15, D14 = 01), 14 LSBs = 0x0000

0111 1111 1111 1111

FREQ0 register write

(D15, D14 = 01), 14 MSBs = 0x3FFF

In some applications, the user does not need to alter all 28 bits

of the frequency register. With coarse tuning, only the 14 MSBs

are altered, while with fine tuning, only the 14 LSBs are altered.

By setting the B28 (D13) control bit to 0, the 28-bit frequency

and the other containing the 14 LSBs. This means that the 14 MSBs

of the frequency word can be altered independent of the 14 LSBs,

and vice versa. Bit HLB (D12) in the control register identifies

which 14 bits are being altered. Examples of this are shown in

Table 10 and Table 11.

Table 10. Writing 0x3FFF to the 14 LSBs of the FREQ1 Register

SDATA Input

Result of Input Word

0000 0000 0000 0000

Control word write (D15, D14 = 00),

B28 (D13) = 0; HLB (D12) = 0, that is, LSBs

1011 1111 1111 1111

FREQ1 REG write (D15, D14 = 10),

14 LSBs = 0x3FFF

Table 11. Writing 0x00FF to the 14 MSBs of the FREQ0 Register

SDATA Input

Result of Input Word

0001 0000 0000 0000

Control word write (D15, D14 = 00),

B28 (D13) = 0, HLB (D12) = 1, that is, MSBs

0100 0000 1111 1111

FREQ0 REG write (D15, D14 = 01),

14 MSBs = 0x00FF

Writing to a Phase Register

When writing to a phase register, Bit D15 and Bit D14 are set to 11.

Bit D13 identifies which phase register is being loaded.

Table 12. Phase Register Bits

D15

D14

D13

D12

D11

MSB 12 PHASE0 bits

LSB

MSB 12 PHASE1 bits

LSB

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