AD9837 datasheet(16/28 Pages) AD

16 / 28 page

AD9837

Data Sheet

Rev. A | Page 16 of 28

RESET FUNCTION

The reset function resets the appropriate internal registers to 0

to provide an analog output of midscale. A reset does not reset

the phase, frequency, or control registers. When the AD9837 is

powered up, the part should be reset (see the Powering Up the

AD9837 section). To reset the AD9837, set the RESET bit to 1.

To take the part out of reset, set the bit to 0. A signal appears at

the DAC output seven or eight MCLK cycles after the RESET

bit is set to 0.

Table 14. Applying the Reset Function

RESET Bit

Result

No reset applied

Internal registers reset

SLEEP FUNCTION

Sections of the AD9837 that are not in use can be powered

down to minimize power consumption by using the sleep

function. The parts of the chip that can be powered down are

the internal clock and the DAC. The bits required for the sleep

function are shown in Table 15.

Table 15. Applying the Sleep Function

SLEEP1 Bit

SLEEP12 Bit

Result

No power-down

DAC powered down

Internal clock disabled

DAC powered down and

internal clock disabled

DAC Powered Down

When the AD9837 is used to output the MSB of the DAC data

only, the DAC is not required. The DAC can be powered down

using the SLEEP12 bit to reduce power consumption.

Internal Clock Disabled

When the internal clock of the AD9837 is disabled, the DAC

output remains at its present value because the NCO is no

longer accumulating. New frequency, phase, and control words

can be written to the part when the SLEEP1 control bit is active.

Because the synchronizing clock (FSYNC) remains active, the

selected frequency and phase registers can also be changed using

the control bits. Setting the SLEEP1 bit to 0 enables the MCLK.

Any changes made to the registers while SLEEP1 was active are

observed at the output after a latency period (see the Latency

Period section).

VOUT PIN

The AD9837 offers a variety of outputs from the chip, all of

which are available from the VOUT pin. The available outputs

are the MSB of the DAC data, a sinusoidal output, or a triangle

output.

The OPBITEN and MODE bits (Bit D5 and Bit D1 in the

control register) are used to determine the output that is

available from the AD9837 (see Table 16).

Table 16. Outputs from the VOUT Pin

OPBITEN Bit

MODE Bit

DIV2 Bit

VOUT Pin Output

Sinusoid

Triangle

DAC data MSB/2

DAC data MSB

Reserved

MSB of the DAC Data

The MSB of the DAC data can be output from the AD9837. By

setting the OPBITEN bit (Bit D5) to 1, the MSB of the DAC data

is available at the VOUT pin. This is useful as a coarse clock

source. This square wave can also be divided by 2 before being

output. The DIV2 bit (Bit D3) in the control register controls

the frequency of this output from the VOUT pin.

Sinusoidal Output

The SIN ROM converts the phase information from the frequency

and phase registers into amplitude information, resulting in a

sinusoidal signal at the output. To obtain a sinusoidal output

from the VOUT pin, set the MODE bit (Bit D1) to 0 and the

OPBITEN bit (Bit D5) to 0.

Triangle Output

The SIN ROM can be bypassed so that the truncated digital output

from the NCO is sent to the DAC. In this case, the output is no

longer sinusoidal. The DAC produces a 10-bit linear triangular

function (see Figure 21). To obtain a triangle output from the

VOUT pin, set the MODE bit (Bit D1) to 1 and the OPBITEN

bit (Bit D5) to 0.

VOUT MIN

VOUT MAX

2π

4π

6π

Figure 21. Triangle Output

POWERING UP THE AD9837

The flowchart in Figure 22 shows the operating routine for the

AD9837. When the AD9837 is powered up, the part should be

reset. This resets the appropriate internal registers to 0 to provide

an analog output of midscale. To avoid spurious DAC outputs

during AD9837 initialization, the RESET bit should be set to 1

until the part is ready to begin generating an output.

A reset does not reset the phase, frequency, or control registers.

These registers will contain invalid data and, therefore, should

be set to known values by the user. The RESET bit should then

be set to 0 to begin generating an output. The data appears on

the DAC output seven or eight MCLK cycles after the RESET

bit is set to 0.

AD9837 Datasheet(PDF) 16 Page - Analog Devices

AD9837 Datasheet(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL