VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

Deserializer/Reclocker at 1.485Gb/s

SMPTE-292M Serializer, Deserializer, and

VSC6511

Page 4

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

4/10/00

G52311-0, Rev 2.0

Table 1: Frame Aligner Output Timing

D[19:0] Databus

As mentioned previously, in Serializer mode D[19:0] is configured as a input. In Deserializer mode,

D[19:0] is configured as an output.

Application Information

The VSC6511 cable driver output is intended to fully comply with the SMPTE-292M cable driver specifi-

cations. This includes an 800mV swing and a return loss of more than 15dB. The circuit shown below shows

how to connect the output of the VSC6511 to the 75 ohm cable and downstream device. The output of the

VSC6511 is actually 1200mV. The output termination circuit shown below attenuates the output signal to

800mV and ensures a return loss better than -15dB. The ISET resistor is 1.78K

D10-19

D0-9

LINE

FRAME

HANC

CRCERR

DATA

DATA

0

0

0

0

---

---

0

0

0

0

DATA

DATA

0

0

0

0

3FF

3FF

00

00

000

000

00

00

000

000

00

00

XYZ

XYZ

0

0

0

0

LN0

LN0

00

00

LN1

LN1

11*0

0

CRC0

CRC0

0

0

0

0

CRC1

CRC1

0

0

0

0 or 1

DATA

DATA

0

0

1

0

---

---

0

0

1

0

DATA

DATA

0

0

1

0

3FF

3FF

00

00

000

000

00

00

000

000

00

00

XYZ

XYZ

0

0

0

0

DATA

DATA

0

0

0

0

DATA

DATA

0

0

0

0

---

---

0

0

0

0

* FRAME is HIGH only if LN0/LN1 indicates the first line of a frame.

** CRCERR is HIGH only during CRC1 if the CRC is incorrect.