© VITESSE SEMICONDUCTOR CORPORATION

Page 11

4/10/00

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VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC6511

Deserializer/Reclocker at 1.485Gb/s

SMPTE-292M Serializer, Deserializer, and

G52311-0, Rev. 2.0

Functional Description: Deserializer Mode

The following functional blocks are used in the Deserializer mode of operation. Please refer to the Func-

tional Description at the beginning of this document for the a description of each of these blocks.

Clock Multiplier Unit (CMU)

Serial Input

Clock Recovery Unit

Deserializer

Descrambler and NRZI Decoder

CRC Checker

Frame Aligner and SAV/EAV output

Figure 6: Receive Timing Waveforms (Deserializer Mode)

Table 5: Receive AC Characteristics (Deserializer Mode)

Note: The RCLK output from the CRU is 40% high and 60% low by design.

Parameters

Description

Min.

Max.

Units

Conditions

TTL Outputs alid prior to

RCLK rise

3.0

—ns.

TTL Outputs valid after

RCLK rise

2.0

—

ns.

TTL Output rise and fall

time

—2.0

ns.

Data acquisition lock time

@ 1.485 Gb/s

—

TBC

ms.

RCLK

D[0:19]

Data Valid

LINE

FRAME

CRCERR