GMS77C1001 datasheet(26/44 Pages) HYNIX

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GMS77C1000/GMS77C1001

July. 2001 Ver. 1.1

10. I/O PORTS

The GMS77C1000/1001 has a 4-bit I/O port(RA) and a 8-

bit I/O port(RB).

All pin have data(RA,RB) and direction(TRISA,TRISB)

registers which can assign these ports as output or input.

A “0” in the port direction registers configure the corre-

sponding port pin as output. Conversely, write “1” to the

corresponding bit to specify it as input pin (Hi-Z state).

For example, to use the even numbered bit of RB as output

ports and the odd numbered bits as input ports, write “55H”

to TRISB register during initial setting as shown in Figure

10-1.

All the port direction registers in the GMS77C1000/1001

have “1” written to them by reset function. This causes all

port as input.

10.1 Port RA

RA is a 4-bit I/O register. Each I/O pin can independently

used as an input or an output through the port direction reg-

ister, TRISA. A “0” in the TRISA register configure the

corresponding port pin as output. Conversely, write “1”to

the corresponding bit to specify it as input pin.

Bits 7-4 are unimplemented and read as '0's.

10.2 Port RB

RB is an 8-bit I/O register. Each I/O pin can independently

used as an input or an output through the port direction reg-

ister, TRISB. A “0” in the TRISB register configure the

corresponding port pin as output. Conversely, write “1”to

the corresponding bit to specify it as input pin.

Note: A read of the ports reads the pins, not the output

data latches. That is, if an output driver on a pin is

enabled and driven high, but the external system is

holding it low, a read of the port will indicate that the

pin is low.

10.3 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Fig-

ure 10-4. All ports may be used for both input and output

operation.

For input operations these ports are non-latching. Any in-

put must be present until read by an input instruction. The

outputs are latched and remain unchanged until the output

latch is rewritten. To use a port pin as output, the corre-

sponding direction control bit (in TRISA, TRISB) must be

cleared (= 0). For use as an input, the corresponding TRIS

bit must be set. Any I/O pin can be programmed individu-

ally as input or output..

10.4 I/O Successive Operations

The actual write to an I/O port happens at the end of an in-

struction cycle, whereas for reading, the data must be valid

at the beginning of the instruction cycle (Figure 10-5).

Therefore, care must be exercised if a write followed by a

read operation is carried out on the same I/O port.

The sequence of instructions should allow the pin voltage

to stabilize (load dependent) before the next instruction,

which causes that file to be read into the CPU, is executed.

FIGURE 10-1 EXAMPLE OF PORT I/O ASSIGNMENT

FIGURE 10-2 RA PORT REGISTERS

PORT RB

OUT IN OU T IN OU T IN OUT IN

Write “55H” to port RB direction register

TRISB

RA RA3

RA2

RA 1

RA0

RA Data Register

RA Direction Register

TRISA

ADDRESS : 05H

RESET VALUE : Undefined

ADDRESS : N/A

RESET VALUE : 0FH

FIGURE 10-3 RB PORT REGISTERS

RB RB7

RB6

RB 5

RB4

RB Data Register

RB Direction Register

TRISB

ADDRESS : 06H

RESET VALUE : Undefined

ADDRESS : N/A

RESET VALUE : FFH

RB3

RB 2

RB1

RB0

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