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ML9261 Datasheet(PDF) 10 Page - OKI electronic componets |
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ML9261 Datasheet(HTML) 10 Page - OKI electronic componets |
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10 / 17 page ![]() ¡ Semiconductor ML9261/62 10/16 — CLK-LS Setup Time ns LS-CLK Setup Time LS-CHG Setup Time LS Pulse Width 50 ns ns ns ns 50 50 50 80 — — — — CHG Pulse Width Driver Output Slew Rate ms ms ms 5.0 5.0 — — — 10 tH (CLK-D) tSU (CLK-LS) tSU (LS-CLK) tSU (LS-CHG) tW (LS) tTHL tTLH tW (CHG) ns 50 — tSU (LS-CL) CL Pulse Width ms 10 — tW (CL) ns —50 tPD, tPRD Driver Output Delay Time ms — 1.0 tDLH ms — 1.0 tDHL (VDD=4.5 to 5.5V, VDISP=40V, Ta=–40 to +85°C) DIN Hold Time LS-CL Setup Time DOUT Delay time Max. Min. Unit Symbol Parameter Condition 150 DIN Setup Time ns 80 ns 50 — tW (CLK) tSU (D-CLK) CLK Pulse Width ns 50 — tSU (L-CLK) During normal operation At display data reset CLK-LS Hold Time ns 50 — tH (CLK-L) At display data reset Load: 30pF ms — 1.0 tDRHL Load: 2.0kW resistance in parallel with 20pF capacitance Load: 2.0kW resistance in parallel with 20pF capacitance AC Characteristics-1 AC Characteristics-2 — CLK-LS Setup Time ns LS-CLK Setup Time LS-CHG Setup Time LS Pulse Width 50 ns ns ns ns 50 50 50 80 — — — — CHG Pulse Width Driver Output Slew Rate ms ms ms 5.0 5.0 — — — 10 tH (CLK-D) tSU (CLK-LS) tSU (LS-CLK) tSU (LS-CHG) tW (LS) tTHL tTLH tW (CHG) ns 50 — tSU (LS-CL) CL Pulse Width ms 10 — tW (CL) ns —50 tPD, tPRD Driver Output Delay Time ms — 3.0 tDLH ms — 3.0 tDHL (VDD=3.0 to 3.6V, VDISP=40V, Ta=–40 to +85°C) DIN Hold Time LS-CL Setup Time DOUT Delay time Max. Min. Unit Symbol Parameter Condition — 50 ns tSU (D-CLK) DIN Setup Time 150 80 ns tW (CLK) CLK Pulse Width During normal operation ns 50 — tSU (L-CLK) At display data reset CLK-LS ns 50 — tH (CLK-L) At display data reset Load: 30pF ms — 3.0 tDRHL Load: 2.0kW resistance in parallel with 20pF capacitance Load: 2.0kW resistance in parallel with 20pF capacitance |
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