SSD1818A datasheet(39/47 Pages) ETC

39 / 47 page

SSD1818A

Rev 1.2

P 39/47 Mar 2004

Solomon Systech

Symbol

Parameter

Min

Typ

Max

Unit

tcycle

Clock Cycle Time

300

tAS

Address Setup Time

tAH

Address Hold Time

tDSW

Write Data Setup Time

tDHW

Write Data Hold Time

tDHR

Read Data Hold Time

tOH

Output Disable Time

tACC

Access Time

140

PWCSL

Chip Select Low Pulse Width (read)

Chip Select Low Pulse Width (write)

120

PWCSH

Chip Select High Pulse Width (read)

Chip Select High Pulse Width (write)

Rise Time

Fall Time

Table 13 - Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -35 to 85°C)

DHR

ACC

Valid Data

DSW

DHW

CSL

CSH

cycle

0-D7

(Read data from driver)

0-D7

(Write data to driver)

CS1

CS2 = 1

D/C

Figure 10 - 8080-series MPU Parallel Interface Characteristics

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