SSD1818A datasheet(13/47 Pages) ETC

13 / 47 page

SSD1818A

Rev 1.2

P 13/47 Mar 2004

Solomon Systech

SPI

This is the input pin to enable the circuitry for providing serial interface. This pin must be connected to low

at any circumstances. When the SPI pin and the P/ S , selection input are both pulled low, the serial

interface is enabled. When the SPI pin is pulled low and the P/ S selection input is pulled high, the

parallel interface is enabled.

NC/TEST0 – TEST2/T0 – T2

These are the No Connection pins. These pins should be left open individually.

Remarks: These pins should not be connected together.

ROW0 - ROW63

These pins provide the Common driving signals to the LCD panel. Please refer to the Table 3 on Page 11

for the COM signal mapping.

SEG0 - SEG103

These pins provide the LCD segment driving signals. The output voltage level of these pins is VDD during

sleep mode or standby mode.

ICONS

There are two ICONS pins (pin137 and 275) on the chip. Both pins output exactly the same signal. The

reason for duplicating these pins is to enhance the flexibility of the LCD layout.

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