AD9785 datasheet(40/62 Pages) AD

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AD9785/AD9787/AD9788

Data Sheet

Rev. C | Page 40 of 62

QUADRATURE MODULATOR

The quadrature modulator is used to mix the carrier signal

generated by the NCO with the upsampled I and Q data

provided by the user at the 16-bit parallel input port of the

device. Figure 58 shows a detailed block diagram of the

quadrature modulator.

The NCO provides a quadrature carrier signal with a frequency

determined by the 32-bit frequency tuning word (FTW) set in

to the upsampled I data and Q data. The generated carrier

signal is mixed via multipliers with the I data and Q data. The

quadrature products are then summed.

Note that the sine output of the NCO contains a mux that

allows negating of the data. The mux is controlled with a

spectral inversion bit that the user stores in an I/O register

(Register 0x01, Bit 10). The default condition is to select

negated sine data.

NUMERICALLY CONTROLLED OSCILLATOR

The NCO generates a complex carrier signal to translate the

input signal to a new center frequency. A complex carrier signal

is a pair of sinusoidal waveforms of the same frequency, offset

90° from each other. The frequency of the complex carrier

signal is set via the Frequency Tuning Word [31:0] value in

calculated as follows:

If {0 ≤ FTW ≤ 231}, use fCENTER = (FTW) (fDACCLK)/232

If {231 < FTW < 232 − 1}, use fCENTER = fDACCLK × (1 − (FTW/232))

A 16-bit phase offset may be added to the output of the phase

accumulator via the serial port. This static phase adjustment

results in an output signal that is offset by a constant angle

relative to the nominal signal. This allows the user to phase

align the NCO output with some external signal, if necessary.

This can be especially useful when NCOs of multiple AD9785/

AD9787/AD9788 devices are programmed for synchronization.

The phase offset allows for the adjustment of the output timing

between the devices. The static phase adjustment is sourced

from the NCO Phase Offset Word [15:0] value located in

By default, when an SPI write is completed for the frequency

tuning word, phase control, DAC gain scaling, or DAC offset

registers (Register 0x0A through Register 0x0D), the operation

of the AD9785/AD9787/AD9788 is immediately updated to

reflect these changes. However, in many applications it may be

more useful to update these registers without changing the

device operation until all these functions can be updated at

once. With the automatic I/O transfer enable bit set low in the

COMM register (Register 0x00, Bit 1), the value of all these

functions is stored in a buffer after the initial SPI write. To

update all these functions simultaneously, Bit 2 of the COMM

require another reset in a later SPI write.

INVERSE SINC FILTER

The inverse sinc filter is implemented as a nine-tap FIR filter. It

is designed to provide greater than ±0.05 dB pass-band ripple

up to a frequency of 0.4 × fDACCLK. To provide the necessary

peaking at the upper end of the pass band, the inverse sinc filter

has an intrinsic insertion loss of 3.4 dB. The tap coefficients are

given in Table 31.

INTERPOLATION

NCO

–1

COSINE

SINE

DATA

FTW [31:0]

SPECTRAL

INVERSION

OUT_I

OUT_Q

–

NCO PHASE OFFSET

WORD [15:0]

Figure 58. Quadrature Modulator Block Diagram

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