AD9785 datasheet(2/62 Pages) AD

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AD9785/AD9787/AD9788

Data Sheet

Rev. C | Page 2 of 62

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Typical Signal Chain......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

Digital Specifications ................................................................... 4

AC Specifications.......................................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 20

Theory of Operation ...................................................................... 21

Serial Port Interface.................................................................... 21

SPI Register Map............................................................................. 24

SPI Register Descriptions .......................................................... 25

Input Data Ports.............................................................................. 33

Single-Port Mode........................................................................ 33

Dual-Port Mode.......................................................................... 33

Input Data Referenced to DATACLK ...................................... 33

Input Data Referenced to REFCLK.......................................... 35

Optimizing the Data Input Timing.......................................... 36

Input Data RAM......................................................................... 37

Digital Datapath ............................................................................. 38

Interpolation Filters ................................................................... 38

Quadrature Modulator .............................................................. 40

Numerically Controlled Oscillator .......................................... 40

Inverse Sinc Filter ....................................................................... 40

Digital Amplitude and Offset Control .................................... 41

Digital Phase Correction........................................................... 41

Device Synchronization................................................................. 42

Synchronization Logic Overview............................................. 42

Synchronizing Devices to a System Clock .............................. 44

Synchronizing Multiple Devices to Each Other..................... 45

Interrupt Request Operation .................................................... 46

Driving the REFCLK Input ........................................................... 47

DAC REFCLK Configuration................................................... 47

Analog Outputs............................................................................... 50

Digital Amplitude Scaling......................................................... 50

Power Dissipation........................................................................... 52

AD9785/AD9787/AD9788 Evaluation Boards........................... 54

Output Configuration................................................................ 54

Digital Picture of Evaluation Board......................................... 54

Evaluation Board Software........................................................ 55

Evaluation Board Schematics ................................................... 56

Outline Dimensions ....................................................................... 62

Ordering Guide .......................................................................... 62

REVISION HISTORY

5/2018—Rev. B to Rev. C

Change to Table 32 ......................................................................... 45

2/2016—Rev. A to Rev. B

Changed SPI_CSB to SPI_CS....................................... Throughout

Changes to General Description Section ...................................... 1

Changes to Figure 2 and Table 6..................................................... 7

Changes to Figure 3 and Table 7..................................................... 9

Changes to Figure 4 and Table 8................................................... 11

Changes to Figure 52...................................................................... 36

Updated Outline Dimensions ....................................................... 62

Changes to Ordering Guide .......................................................... 62

2/2009—Rev. 0 to Rev. A

Added Settling Time, to Within ±0.5 LSBs Parameter, Table 1...3

Added REFCLK Frequency Range, PLL Enabled Parameter,

Table 2 .................................................................................................4

Changes to SPI_SDIO—Serial Data I/O Section ....................... 23

Changes to Table 9.......................................................................... 24

Changes to Table 11 ....................................................................... 26

Changes to Table 12 ....................................................................... 27

Changes to Table 13 ....................................................................... 28

Changes to Table 22 ....................................................................... 32

Changes to Dual-Port Mode Section ........................................... 33

Changes to Input Data RAM Section .......................................... 37

Changes to Digital Amplitude and Offset Control Section ...... 41

Changes to Direct Clocking Section............................................ 47

1/2008—Revision 0: Initial Version

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