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Data Sheet

AD9785/AD9787/AD9788

Rev. C | Page 29 of 62

The PLL control (PLLCTL) register comprises three bytes located at Address 0x04. These bits are routed directly to the periphery of the

digital logic. No digital functionality within the main digital block is required.

Table 14. PLL Control (PLLCTL) Register

Address

Bit

Name

Description

0x04

[23:21]

VCO Control Voltage

[2:0]

000 to 111, proportional to voltage at VCO, control voltage input (readback only). A value of

011 indicates that the VCO control voltage is centered.

[20:16]

PLL Loop Bandwidth

[4:0]

These bits control the bandwidth of the PLL filter. Increasing the value lowers the loop

bandwidth. Set to 01111 for optimal performance.

[15]

PLL Enable

0: Default. With PLL off, the DAC sample clock is sourced directly by the REFCLK input.

1: With PLL on, the DAC clock is synthesized internally from the REFCLK input via the PLL

clock multiplier. See the Clock Multiplication section for details.

[14:13]

PLL VCO Divisor [1:0]

Sets the value of the VCO output divider, which determines the ratio of the VCO output

frequency to the DAC sample clock frequency, fVCO/fDACCLK.

00: fVCO/fDACCLK = 1.

01: fVCO/fDACCLK = 2.

10: fVCO/fDACCLK = 4.

11: fVCO/fDACCLK = 8.

[12:11]

PLL Loop Divisor [1:0]

Sets the value of the DACCLK divider, which determines the ratio of the DAC sample clock

frequency to the REFCLK frequency, fDACCLK/fREFCLK.

00: fDACCLK/fREFCLK = 2.

01: fDACCLK/fREFCLK = 4.

10: fDACCLK/fREFCLK = 8.

11: fDACCLK/fREFCLK = 16.

[10:8]

PLL Bias [2:0]

These bits control the VCO bias current. Set to 011 for optimal performance.

[7:2]

PLL Band Select [5:0]

These bits set the operating frequency of the VCO. For further details, refer to Table 35.

[1:0]

PLL VCO Drive [1:0]

These bits control the signal strength of the VCO output. Set to 11 for optimal performance.

The I DAC control register comprises two bytes located at Address 0x05. These bits are routed directly to the periphery of the digital

logic. No digital functionality within the main digital block is required.

Table 15. I DAC Control Register

Address

Bit

Name

Description

0x05

[15]

I DAC Sleep

0: Default. If the I DAC sleep bit is cleared, the I DAC is active.

1: If the I DAC sleep bit is set, the I DAC is inactive and enters a low power state.

[14]

I DAC Power-Down

0: Default. If the I DAC power-down bit is cleared, the I DAC is active.

1: If the I DAC power-down bit is set, the I DAC is inactive and enters a low power state.

[13:10]

Reserved

Reserved for future use.

[9:0]

I DAC Gain

Adjustment

These bits are the I DAC gain adjustment bits.

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