LM2746 datasheet(11/24 Pages) NSC

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Application Information (Continued)

A desired delay time t

DELAY between the startup of the

master supply output voltage and the LM2746 output voltage

can be set based on the SD pin low-to-high threshold V

SD-IH

and the slew rate of the voltage at the SD pin, SR

SD:

DELAY =VSD-IH /SRSD

Note again, that in Figure 4, the LM2746’s output voltage

has been represented symbolically as V

OUT2, i.e. without

explicitly showing the power components.

SD-IH is typically 1.08V and SRSD is the slew rate of the SD

pin voltage. The values of the sequencing divider resistors

S1 and RS2 set the SRSD based on the master supply

output voltage slew rate, SR

OUT1, using the following equa-

tion:

For example, if the master supply output voltage slew rate

were 1V/ms and the desired delay time between the startup

of the master supply and LM2746 output voltage were 5ms,

then the desired SD pin slew rate would be (1.08V/5ms) =

0.216V/ms. Due to the internal impedance of the SD pin, the

maximum recommended value for R

S2 is 1k

Ω. To achieve

the desired slew rate, R

S1 would then be 274

Ω. A timing

diagram for this example is shown in Figure 5.

SD PIN IMPEDANCE

When connecting a resistor divider to the SD pin of the

LM2746 some care has to be taken. Once the SD voltage

goes above V

SD-IH, a 17 µA pull-up current is activated as

shown in Figure 6. This current is used to create the internal

hysteresis ()170mV); however, high external impedances

will affect the SD pin logic thresholds as well. The external

impedance used for the sequencing divider network should

preferably be a small fraction of the impedance of the SD pin

for good performance (around 1k

Ω).

MOSFET GATE DRIVERS

The LM2746 has two gate drivers designed for driving

N-channel MOSFETs in a synchronous mode. Note that

unlike most other synchronous controllers, the bootstrap

capacitor of the LM2746 provides power not only to the

driver of the upper MOSFET, but the lower MOSFET driver

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FIGURE 4. Sequencing Circuit

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FIGURE 5. Delay for Sequencing

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FIGURE 6. SD Pin Logic

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