LTC2249 datasheet(14/20 Pages) LINER

14 / 20 page

LTC2249

2249f

The lower limit of the LTC2249 sample rate is determined

by droop of the sample-and-hold circuits. The pipelined

architecture of this ADC relies on storing analog signals on

small valued capacitors. Junction leakage will discharge

the capacitors. The specified minimum operating fre-

quency for the LTC2249 is 1Msps.

DIGITAL OUTPUTS

Digital Output Buffers

Figure 12 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OVDD and OGND, iso-

lated from the ADC power and ground. The additional

N-channel transistor in the output driver allows operation

down to low voltages. The internal resistor in series with

the output makes the output appear as 50Ω to external

circuitry and may eliminate the need for external damping

resistors.

As with all high speed/high resolution converters, the

digital output loading can affect the performance. The

digital outputs of the LTC2249 should drive a minimal

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. The output

should be buffered with a device such as an ALVCH16373

CMOS latch. For full speed operation the capacitive load

should be kept under 10pF.

Lower OVDD voltages will also help reduce interference

from the digital outputs.

Data Format

Using the MODE pin, the LTC2249 parallel digital output

can be selected for offset binary or 2’s complement

format. Connecting MODE to GND or 1/3VDD selects

straight binary output format. Connecting MODE to

2/3VDD or VDD selects 2’s complement output format.

An external resistor divider can be used to set the 1/3VDD

or 2/3VDD logic values. Table 1 shows the logic states for

the MODE pin.

Figure 12. Digital Output Buffer

LTC2249

2249 F12

OVDD

VDD

0.1µF

43Ω

TYPICAL

DATA

OUTPUT

OGND

OVDD

0.5V

TO VDD

PREDRIVER

LOGIC

DATA

FROM

LATCH

Table 1. MODE Pin Function

Clock Duty

MODE Pin

Output Format

Cycle Stablizer

Straight Binary

Off

1/3VDD

Straight Binary

2/3VDD

2’s Complement

VDD

2’s Complement

Off

Overflow Bit

When OF outputs a logic high the converter is either

overranged or underranged.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OVDD, should be tied

to the same power supply as for the logic being driven. For

example if the converter is driving a DSP powered by a 1.8V

supply, then OVDD should be tied to that same 1.8V supply.

OVDD can be powered with any voltage from 500mV up to

the VDD of the part. OGND can be powered with any voltage

from GND up to 1V and must be less than OVDD. The logic

outputs will swing between OGND and OVDD.

Output Enable

The outputs may be disabled with the output enable pin, OE.

OE high disables all data outputs including OF. The data ac-

cess and bus relinquish times are too slow to allow the

outputs to be enabled and disabled during full speed op-

eration. The output Hi-Z state is intended for use during long

periods of inactivity.

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