AD5689R datasheet(20/28 Pages) AD

20 / 28 page

AD5689R/AD5687R

Data Sheet

Rev. B | Page 20 of 28

SERIAL INTERFACE

The AD5689R/AD5687R have a 3-wire serial interface

(SYNC, SCLK, and SDIN) that is compatible with SPI, QSPI™,

and MICROWIRE® interface standards as well as most DSPs.

See Figure 2 for a timing diagram of a typical write sequence.

The AD5689R/AD5687R contain an SDO pin that allows

the user to daisy-chain multiple devices together (see the

Daisy-Chain Operation section) or read back data.

Input Shift Register

The input shift register of the AD5689R/AD5687R is 24 bits

wide, and data is loaded MSB first (DB23). The first four bits

are the command bits, C3 to C0 (see Table 9), followed by

the 4-bit DAC address bits, composed of DAC B, DAC A,

and two don’t care bits that must be set to 0 (see Table 8).

Finally, the data-word completes the input shift register.

The data-word comprises 16-bit or 12-bit input code, followed

by zero don’t care bits (for the AD5689R) or four don’t care bits

(for the AD5687R), as shown in Figure 43 and Figure 44, respec-

tively). These data bits are transferred to the input shift register

on the 24 falling edges of SCLK and updated on the rising edge

of SYNC.

Commands can be executed on individual DAC channels or on

both DAC channels, depending on the address bits selected.

Table 8. Address Commands

Address (n)

Selected DAC Channel

DAC B

DAC A

DAC B

DAC A and DAC B

Table 9. Command Definitions

Command

Description

No operation

Write to Input Register n (dependent on LDAC)

Update DAC Register n with contents of Input Register n

Write to and update DAC Channel n

Power down/power up DAC

Hardware LDAC mask register

Software reset (power-on reset)

Internal reference setup register

Set up DCEN register (daisy-chain enable)

Set up readback register (readback enable)

Reserved

…

Reserved

No operation in daisy-chain mode

ADDRESS BITS

COMMAND BITS

DAC

D15 D14 D13 D12 D11 D10

DB23 (MSB)

DB0 (LSB)

DATA BITS

Figure 43. AD5689R Input Shift Register Content

DAC

D11 D10

ADDRESS BITS

COMMAND BITS

DB23 (MSB)

DB0 (LSB)

DATA BITS

Figure 44. AD5687R Input Shift Register Content

AD5689R Datasheet(PDF) 20 Page - Analog Devices

AD5689R Datasheet(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL