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AD5689R Datasheet(PDF) 24 Page - Analog Devices

Part # AD5689R
Description  Dual, 16-/12-Bit nanoDAC
PDF  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5689R Datasheet(HTML) 24 Page - Analog Devices

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AD5689R/AD5687R
Data Sheet
Rev. B | Page 24 of 28
HARDWARE RESET (RESET)
RESET is an active low reset that allows the outputs to be cleared
to either zero scale or midscale. The clear code value is user
selectable via the power-on reset select pin (RSTSEL). RESET
must be kept low for a minimum amount of time to complete
the operation (see Figure 2). When the RESET signal is returned
high, the output remains at the cleared value until a new value is
programmed. The outputs cannot be updated with a new value
while the RESET pin is low. There is also a software executable
reset function that resets the DAC to the power-on reset code.
Command 0110 is designated for this software reset function
(see Table 9). Any events on LDAC during a power-on reset are
ignored. If the RESET pin is pulled low at power-up, the device
does not initialize correctly until the pin is released.
RESET SELECT PIN (RSTSEL)
The AD5689R/AD5687R contain a power-on reset circuit that
controls the output voltage during power-up. When the RSTSEL
pin is connected low (to GND), the output powers up to zero
scale. Note that this is outside the linear region of the DAC.
When the RSTSEL pin is connected high (to VLOGIC), VOUTX
powers up to midscale. The output remains powered up at this
level until a valid write sequence is sent to the DAC.
To ensure that the RSTSEL pin functions correctly, a power
sequence must be followed. Power up VLOGIC first, before VDD;
otherwise, VOUT remains at zero scale.
INTERNAL REFERENCE SETUP
Command 0111 is reserved for setting up the internal reference
(see Table 9). By default, the on-chip reference is on at power-up.
To reduce the supply current, this reference can be turned off by
setting the software-programmable bit, DB0, as shown in Table 17.
Table 16 shows how the state of the bit corresponds to the mode
of operation.
Table 16. Reference Setup Register
Internal Reference
Setup Register (DB0)
Action
0
Reference on (default)
1
Reference off
SOLDER HEAT REFLOW
As with all IC reference voltage circuits, the reference value
experiences a shift induced by the soldering process. Analog
Devices, Inc., performs a reliability test, called precondition,
that mimics the effect of soldering a device to a board. The
output voltage specification that is listed in Table 2 includes the
effect of this reliability test.
Figure 48 shows the effect of solder heat reflow (SHR) as
measured through the reliability test (precondition).
60
0
10
20
30
40
50
2.498
2.499
2.500
2.501
2.502
VREF (V)
POSTSOLDER
HEAT REFLOW
PRESOLDER
HEAT REFLOW
Figure 48. SHR Reference Voltage Shift
LONG-TERM TEMPERATURE DRIFT
Figure 49 shows the change in the VREF (ppm) value after
1000 hours at 25°C ambient temperature.
140
120
100
80
60
40
20
0
0
100
200
300
400
500
600
700
800
900 1000
–20
Figure 49. Reference Drift Through to 1000 Hours
Table 17. 24-Bit Input Shift Register Contents for Internal Reference Setup Command1
DB23
(MSB)
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB1
DB0 (LSB)
0
1
1
1
X
X
X
X
X
1 or 0
Command bits (C3 to C0)
Address bits (A3 to A0)
Don’t care
Reference setup register
1 X = don’t care.



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