AD5697R datasheet(6/27 Pages) AD

6 / 27 page

AD5697R

Data Sheet

Rev. B | Page 6 of 27

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; 1.62 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.

Table 4.

Parameter1

Min

Max

Unit

Test Conditions/Comments

2.5

µs

SCL cycle time

0.6

µs

SCL high time, tHIGH

1.3

µs

SCL low time, tLOW

0.6

µs

Start/repeated start condition hold time, tHD,STA

100

Data setup time, tSU,DAT

t62

0.9

µs

Data hold time, tHD,DAT

0.6

µs

Setup time for repeated start, tSU,STA

0.6

µs

Stop condition setup time, tSU,STO

1.3

µs

Bus free time between a stop and a start condition, tBUF

t10

300

Rise time of SCL and SDA when receiving, tR

t11

20 + 0.1CB3

300

Fall time of SDA and SCL when transmitting/receiving, tF

t12

LDAC pulse width

t13

400

SCL rising edge to LDAC rising edge

CB3

400

Capacitive load for each bus line

Guaranteed by design and characterization; not production tested.

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum of the SCL signal) to bridge the undefined region of the

falling edge of the SCL.

CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.

Figure 2. 2-Wire Serial Interface Timing Diagram

SCL

SDA

LDAC1

LDAC2

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

NOTES

1ASYNCHRONOUS LDAC UPDATE MODE.

2SYNCHRONOUS LDAC UPDATE MODE.

t13

t11

t10

t12

AD5697R Datasheet(PDF) 6 Page - Analog Devices

AD5697R Datasheet(HTML) 6 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Datasheet Download

Link URL