UVLO1

UV2

UV1

IN(on)

UVLO1

V

1.5 V

R

R

340 k

68 k

V

V

9 V 1.5 V

˜

: ˜

:

UVLO2

IN(on)

IN(off)

UVLO1

UV1

UVLO

V

1.45 V

V

V

9 V

7 V

V

1.5 V

R

340k

I

5 $

˜

˜

:

OUT

D

PS

FB

V

V

N

15 V

0.3 V 1

R

154 k

0.1 mA

0.1 mA

˜

˜

:

IN(max)

D2-REV

OUT2

PS

V

V

V

70 V 0.55

8 V

46.5 V

N

t

˜

IN(max)

D1-REV

OUT1

PS

V

70 V

V

V

15 V

85 V

N

1

t

21

LM5180-Q1

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SNVSB07A – JULY 2018 – REVISED AUGUST 2018

Product Folder Links: LM5180-Q1

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Copyright © 2018, Texas Instruments Incorporated

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Choose a 200-V, 1-A ultra-fast switching diode and a 100-V, 1-A Schottky diode for the positive and negative

outputs, respectively, to allow some margin for inevitable voltage overshoot and ringing related to leakage

inductance and diode capacitance. If needed, use a diode RC snubber circuit, for example 100 Ω and 22 pF, to

mitigate such overshoot and ringing.

8.2.2.2.3

a low-ESR ceramic input capacitor sized according to Equation 23 for the RMS ripple current given by

Equation 24. In this design example, choose a 4.7-µF, 100-V ceramic input capacitor with X7S dielectric and

1210 footprint.

8.2.2.2.4

Install a 154-kΩ resistor from SW to FB based on an output voltage setpoint of 15 V (plus a flyback diode voltage

drop) reflected to the primary by a transformer turns ratio of unity.

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8.2.2.2.5

the upper and lower UVLO resistors using Equation 35 and Equation 36.

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