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Specifications subject to change without notice

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Interface I/O

• 12 TTL inputs or 6 RS-422 differential inputs

• 4 TTL outputs or 2 RS-422 outputs

• 1 USB interface

• 1 JTAG interface

• 1 BITE (Built-In Test Equipment) output

BITE signal is controlled by the user application and is OR’ed with the board power supply status. This signal can be configured as

open-drain or as dry contact.

Signal Generator

The unit generates the output signal based on a DDS (Direct Digital Synthesizer) scheme. A sine waveform is stored in a LUT (Look-Up

Table) and then is swept to generate the output signal. The main advantage of this architecture is the speed: output signal can change

its frequency in less than 10 ns. Each DDS block is composed of a DDS Core Block and a high speed DAC to perform the digital to analog

conversion.

The core of the DDS is implemented inside the FPGA and interacts with the User Application using 3 data lines that allow to change

frequency, phase and gain on real-time. This block also interacts with a high speed DAC which is responsible of the digital to analog

conversion.

Finally, the user can either route each DDS directly to the module’s output or fed them to an internal IQ modulator for up conversion

purpose.

Signal Generator

I Output

100 kHz – 500 MHz

CLK Mod

Mod Output

3 – 4 GHz

Q Output

100 kHz – 500 MHz

DDS IQ

I/Q Output

100 kHz – 500 MHz

FPGA

DDS Core

Gain

Phase

Frequency

DAC