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Specifications subject to change without notice

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Sectorized Radar Signal generator (S Band): As the previous cases, a trigger signal is used to start emission. Two channels are used to

upconvert the output using the IQ Modulator. The antenna encoder is fed to module in order to have a sectorized configuration. An SPI

interface is also provided to let the user choose the desired waveform. Output is directly upconverted to the Radar’s operating

frequency.

Clocking: The module proposes several clocking schemes. An internal 20 MHz oscillator provides the reference to two PLLs. One have 2

GHz VCO for the DDS clock and the other 3.5 GHz VCO for the IQ Modulator. However, the reference for each PLL can be provided

externally in case of coherent generation. Finally, the user can input directly the clock without using the internal PLLs.

All these clocking possibilities are set using the User application providing the user a very flexible way to adapt clocking to its own final

application.

CLK Mod

FPGA

DDS

Core

Phase

DAC

Correction

s

Gain

Antenna

Encoder

Trigger

Frequency

Chip

LUT

Phase + 90°

DAC

Gain

DDS

Core

Frequency

Controller

SPI Interface

Output

Corrections

CLK Mod

CLK DDS

VCO

2 GHz

PLL

20 MHz

Oscillator

J20

Clk DAC Ext

VCO

3.5

GHz

PLL

J22

Clk Mod Ext