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AD5428/AD5440/AD5447

Data Sheet

Rev. D | Page 16 of 32

GENERAL DESCRIPTION

DAC SECTION

The AD5428/AD5440/AD5447 are CMOS 8-, 10-, and 12-bit,

dual-channel, current output DACs consisting of a standard

inverting R-2R ladder configuration. Figure 37 shows a simplified

diagram for a single channel of the 8-bit AD5428. The feedback

resistor RFBA has a value of R. The value of R is typically 10 kΩ

(with a minimum of 8 kΩ and a maximum of 12 kΩ). If IOUT1

and AGND are kept at the same potential, a constant current

flows into each ladder leg, regardless of digital input code.

Therefore, the input resistance presented at VREFA is always

constant and nominally of value R. The DAC output (IOUT) is

code-dependent, producing various resistances and

capacitances. When choosing an external amplifier, take into

account the variation in impedance generated by the DAC on

the amplifier’s inverting input node.

VREF

DAC DATA LATCHES

AND DRIVERS

RFBA

IOUTA

AGND

Figure 37. Simplified Ladder

Access is provided to the VREF, RFB, and IOUT terminals of DAC A

and DAC B, making the devices extremely versatile and

allowing them to be configured in several operating modes,

such as unipolar output mode, 4-quadrant multiplication

bipolar mode, or single-supply mode. Note that a matching

switch is used in series with the internal RFBA feedback resistor.

If users attempt to measure RFBA, power must be applied to VDD

to achieve continuity.

CIRCUIT OPERATION

Unipolar Mode

Using a single op amp, these devices can easily be configured to

provide 2-quadrant multiplying operation or a unipolar output

voltage swing, as shown in Figure 38. When an output amplifier

is connected in unipolar mode, the output voltage is given by

VOUT

= −VREF × D/2n

where:

D is the fractional representation of the digital word loaded to

the DAC.

D = 0 to 255 (8-bit

AD5428)

= 0 to 1023 (10-bit AD5440)

= 0 to 4095 (12-bit AD5447)

n is the resolution of the DAC.

Note that the output voltage polarity is opposite to the VREF

polarity for dc reference voltages. These DACs are designed to

operate with either negative or positive reference voltages. The

VDD power pin is only used by the internal digital logic to drive

the on and off states of the DAC switches.

These DACs are also designed to accommodate ac reference

input signals in the range of –10 V to +10 V.

With a fixed 10 V reference, the circuit in Figure 38 gives a

unipolar 0 V to –10 V output voltage swing. When VIN is an ac

signal, the circuit performs 2-quadrant multiplication.

Table 7 shows the relationship between digital code and the

expected output voltage for unipolar operation using the 8-bit

AD5428.

Table 7. Unipolar Code

Digital Input

Analog Output (V)

1111 1111

–VREF (255/256)

1000 0000

–VREF(128/256) = –VREF/2

0000 0001

–VREF (1/256)

0000 0000

–VREF (0/256) = 0

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