AD5428 datasheet(18/32 Pages) AD

18 / 32 page

AD5428/AD5440/AD5447

Data Sheet

Rev. D | Page 18 of 32

Bipolar Operation

In some applications, it may be necessary to generate full 4-quad-

rant multiplying operation or a bipolar output swing. This can

easily be accomplished by using another external amplifier and

some external resistors, as shown in Figure 39. In this circuit, the

second amplifier, A2, provides a gain of 2. Biasing the external

amplifier with an offset from the reference voltage results in full

4-quadrant multiplying operation. The transfer function of this

circuit shows that both negative and positive output voltages are

created as the input data (D) is incremented from Code 0 (VOUT =

−VREF) to midscale (VOUT = 0 V) to full scale (VOUT = +VREF).

When connected in bipolar mode, the output voltage is given by



REF

OUT







1

where:

D is the fractional representation of the digital word loaded to

the DAC.

D = 0 to 255 (AD5428)

= 0 to 1023 (AD5440)

= 0 to 4095 (AD5447)

n is the number of bits.

When VIN is an ac signal, the circuit performs 4-quadrant

multiplication. Table 8 shows the relationship between digital

code and the expected output voltage for bipolar operation

using the 8-bit AD5428.

Table 8. Bipolar Code

Digital Input

Analog Output (V)

1111 1111

+VREF (127/128)

1000 0000

0000 0001

–VREF (127/128)

0000 0000

–VREF (128/128)

Stability

In the I-to-V configuration, the IOUT of the DAC and the inverting

node of the op amp must be connected as close as possible, and

proper PCB layout techniques must be used. Because every code

change corresponds to a step function, gain peaking may occur

if the op amp has limited gain bandwidth product (GBP) and

there is excessive parasitic capacitance at the inverting node.

This parasitic capacitance introduces a pole into the open-loop

response, which can cause ringing or instability in the closed-

loop applications circuit.

An optional compensation capacitor, C1, can be added in parallel

with RFBA for stability, as shown in Figure 38 and Figure 39. Too

small a value of C1 can produce ringing at the output, whereas

too large a value can adversely affect the settling time. C1 should

be found empirically, but 1 pF to 2 pF is generally adequate for

the compensation.

CONTROL

LOGIC

INPUT

BUFFER

DATA

INPUTS

IOUTA

DB0

DAC A/B

R/W

DGND

DB7

DB9

DB11

IOUTB

AGND

AD5428/AD5440/AD5447

LATCH

AGND

8-/10-/12-BIT

R-2R DAC A

8-/10-/12-BIT

R-2R DAC B

POWER-ON

RESET

VDD

VREFA

VINA

(±10V)

VREFB

RFBA

RFBB

RR21

VOUTA

R11

VINB

(±10V)

R31

R62

20k



20k



20k



R11



R12



R72

10k



R92

10k



R102

20k



C13

AGND

VOUTB

R41

C23

1R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUTA = 0V WITH CODE 10000000 IN DAC A LATCH.

ADJUST R3 FOR VOUTB = 0V WITH CODE 10000000 IN DAC B LATCH.

2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7 AND R9, R10.

3C1, C2 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER.

Figure 39. Bipolar Operation (4-Quadrant Multiplication)

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