AD5680 datasheet(3/20 Pages) AD

3 / 20 page

Data Sheet

AD5680

Rev. C | Page 3 of 20

SPECIFICATIONS

VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted.

Table 1.

B Grade1

Parameter

Min

Typ

Max

Unit

Conditions/Comments

STATIC PERFORMANCE2

Resolution

Bits

Relative Accuracy

±32

±64

LSB

Differential Nonlinearity3

±1

LSB

Measured in 50 Hz system bandwidth

±2

LSB

Measured in 300 Hz system bandwidth

Zero-Code Error

All 0s loaded to DAC register

Full-Scale Error

−0.2

−1

% FSR

All 1s loaded to DAC register

Offset Error

±10

Gain Error

±1.5

% FSR

Zero-Code Error Drift

±2

μV/°C

Gain Temperature Coefficient

±2.5

ppm

Of FSR/°C

DC Power Supply Rejection Ratio

−100

DAC code = midscale; VDD = 5 V ± 10%

OUTPUT CHARACTERISTICS3

Output Voltage Range

VDD

Output Voltage Settling Time

μs

¼ to ¾ scale change settling to ±8 LSB,

RL = 2 kΩ; 0 pF < CL < 200 pF

Slew Rate

1.5

V/μs

¼ to ¾ scale

Capacitive Load Stability

RL = ∞

RL = 2 kΩ

Output Noise Spectral Density4

nV/√Hz

DAC code = midscale, 10 kHz

Output Noise (0.1 Hz to 10 Hz)4

μV p-p

DAC code = midscale

Total Harmonic Distortion (THD)4

−80

VREF = 2 V ± 300 mV p-p, f = 200 Hz

Digital-to-Analog Glitch Impulse

nV-s

1 LSB change around major carry

Digital Feedthrough

0.2

nV-s

DC Output Impedance

0.5

Short-Circuit Current4

VDD = 5 V

REFERENCE INPUT

Reference Current

μA

VREF = VDD = 5 V

Reference Input Range5

0.75

VDD

Reference Input Impedance

125

kΩ

LOGIC INPUTS3

Input Current

±2

μA

All digital inputs

VINL, Input Low Voltage

0.8

VDD = 5 V

VINH, Input High Voltage

VDD = 5 V

Pin Capacitance

POWER REQUIREMENTS

VDD

4.5

5.5

All digital inputs at 0 V or VDD

IDD (Normal Mode)

DAC active and excluding load current

VDD = 4.5 V to 5.5 V

325

450

μA

VIH = VDD and VIL = GND

POWER EFFICIENCY

IOUT/IDD

ILOAD = 2 mA, VDD = 5 V

1 Temperature range for B version is −40°C to +105°C, typical at +25°C.

2 DC specifications tested with the outputs unloaded, unless otherwise stated. Linearity calculated using a reduced code range of 2048 to 260,096.

3 Guaranteed by design and characterization; not production tested.

4 Output unloaded.

5 Reference input range at ambient where maximum DNL specification is achievable.

AD5680 Datasheet(PDF) 3 Page - Analog Devices

AD5680 Datasheet(HTML) 3 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL