PCA9554

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8

Acknowledge

After a successful data transfer, each receiving device is

required to generate an acknowledge. The acknowledging

device pulls down the SDA line during the ninth clock cycle,

signaling that it received the 8 bits of data. The SDA line

remains stable LOW during the HIGH period of the

acknowledge related clock pulse (Figure 6).

The PCA9554 responds with an acknowledge after

receiving a START condition and its slave address. If the

device has been selected along with a write operation, it

responds with an acknowledge after receiving each 8−bit

byte.

When the PCA9554 begins a READ mode it transmits 8

bits of data, releases the SDA line, and monitors the line for

an acknowledge. Once it receives this acknowledge, the

PCA9554 will continue to transmit data. If no acknowledge

is sent by the Master, the device terminates data transmission

and waits for a STOP condition. The master must then issue

a STOP condition to return the PCA9554 to the standby

power mode and place the device in a known state.

Registers and Bus Transactions

The PCA9554 consists of an input port register, an output

port

register,

a

polarity

inversion

register

and

a

configuration register. Table 7 shows the register address

table. Tables 8 to 11 list Register 0 through Register 3

information.

Table 7. REGISTER COMMAND BYTE

Command

(hex)

Protocol

Function

0x00

Read byte

Input port register

0x01

Read/write byte

Output port register

0x02

Read/write byte

Polarity inversion register

0x03

Read/write byte

Configuration register

The command byte is the first byte to follow the device

address byte during a write/read bus transaction. The

register command byte acts as a pointer to determine which

register will be written or read.

The input port register is a read only port. It reflects the

incoming logic levels of the I/O pins, regardless of whether

the pin is defined as an input or an output by the

configuration register. Writes to the input port register are

ignored.

Table 8. REGISTER 0 – INPUT PORT REGISTER

bit

default

1

1

1

1

1

1

1

1

Table 9. REGISTER 1 – OUTPUT PORT REGISTER

bit

default

1

1

1

1

1

1

1

1

Table 10. REGISTER 2 –

POLARITY INVERSION REGISTER

bit

default

0

0

0

0

0

0

0

0

Table 11. REGISTER 3 – CONFIGURATION REGISTER

bit

default

1

1

1

1

1

1

1

1

Figure 8. Acknowledge Timing

18

9

START

SCL FROM

MASTER

BUS RELEASE DELAY (TRANSMITTER)

ACK DELAY

ACK SETUP

BUS RELEASE DELAY (RECEIVER)

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER