AD5429 datasheet(20/28 Pages) AD

20 / 28 page

AD5429/AD5439/AD5449

Data Sheet

Rev. F | Page 20 of 28

SERIAL INTERFACE

The AD5429/AD5439/AD5449 have an easy-to-use, 3-wire

interface that is compatible with SPI, QSPI, MICROWIRE, and

most DSP interface standards. Data is written to the device in

16-bit words. Each 16-bit word consists of four control bits and

eight, 10, or 12 data bits, as shown in Figure 43 through Figure 45.

Low Power Serial Interface

To minimize the power consumption of the device, the interface

powers up fully only when the device is being written to, that is,

on the falling edge of SYNC. The SCLK and SDIN input buffers

are powered down on the rising edge of SYNC.

DAC Control Bit C3 to Control Bit C0

Control Bit C3 to Control Bit C0 allow control of various functions

of the DAC, as shown in Table 11. The default settings of the DAC

at power-on are such that data is clocked into the shift register

on falling clock edges and daisy-chain mode is enabled. The device

powers on with a zero-scale load to the DAC register and IOUT lines.

The DAC control bits allow the user to adjust certain features at

power-on. For example, daisy-chaining can be disabled if not in

use, an active clock edge can be changed to a rising edge, and DAC

output can be cleared to either zero scale or midscale. The user

can also initiate a readback of the DAC register contents for veri-

fication.

Control Register (Control Bits = 1101)

While maintaining software compatibility with single-channel

current output DACs (AD5426/AD5432/AD5443), these DACs

also feature additional interface functionality. Set the control bits

to 1101 to enter control register mode. Figure 46 shows the

contents of the control register, the functions of which are

described in the following sections.

SDO Control (SDO1 and SDO2)

The SDO bits enable the user to control the SDO output driver

strength, disable the SDO output, or configure it as an open-drain

driver. The strength of the SDO driver affects the timing of t12,

and, when stronger, allows a faster clock cycle.

Table 10. SDO Control Bits

SDO2

SDO1

Function Implemented

Full SDO driver

Weak SDO driver

SDO configured as open drain

Disable SDO output

Daisy-Chain Control (DSY)

DSY allows the enabling or disabling of daisy-chain mode.

A 1 enables daisy-chain mode; a 0 disables daisy-chain mode.

When disabled, a readback request is accepted; SDO is auto-

matically enabled; the DAC register contents of the relevant

DAC are clocked out on SDO; and, when complete, SDO is

disabled again.

Hardware CLR Bit (HCLR)

The default setting for the hardware CLR bit is to clear the registers

and DAC output to zero code. A 1 in the HCLR bit allows the

CLR pin to clear the DAC outputs to midscale, and a 0 clears to

zero scale.

Active Clock Edge (SCLK)

The default active clock edge is a falling edge. Write a 1 to this

bit to clock data in on the rising edge, or a 0 to clock it in on the

falling edge.

DATA BITS

CONTROL BITS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB0 (LSB)

DB15 (MSB)

Figure 43. AD5429 8-Bit Input Shift Register Contents

DATA BITS

CONTROL BITS

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB0 (LSB)

DB15 (MSB)

Figure 44. AD5439 10-Bit Input Shift Register Contents

DATA BITS

CONTROL BITS

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB0 (LSB)

DB15 (MSB)

Figure 45. AD5449 12-Bit Input Shift Register Contents

CONTROL BITS

SDO2

SDO1

DSY

HCLR

SCLK

DB0 (LSB)

DB15 (MSB)

Figure 46. Control Register Loading Sequence

AD5429 Datasheet(PDF) 20 Page - Analog Devices

AD5429 Datasheet(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL