AD5429 datasheet(23/28 Pages) AD

23 / 28 page

Data Sheet

AD5429/AD5439/AD5449

Rev. F | Page 23 of 28

80C51/80L51-to-AD5429/AD5439/AD5449 Interface

A serial interface between the DAC and the 80C51/80L51 is

shown in Figure 51. TxD of the 80C51/80L51 drives SCLK of

the DAC serial interface, and RxD drives the serial data line, SDIN.

P1.1 is a bit-programmable pin on the serial port and is used to

drive SYNC. When data is to be transmitted to the switch, P1.1

is taken low. The 80C51/80L51 transmit data in 8-bit bytes only;

therefore, only eight falling clock edges occur in the transmit cycle.

To load data correctly to the DAC, P1.1 is left low after the first

eight bits are transmitted, and then a second write cycle is initiated

to transmit the second byte of data. Data on RxD is clocked out

of the microcontroller on the rising edge of TxD and is valid on

the falling edge of TxD. As a result, no glue logic is required

between the DAC and microcontroller interface. P1.1 is taken

high following the completion of this cycle. The 80C51/80L51

provide the LSB of the SBUF register as the first bit in the data

stream. The DAC input register requires its data with the MSB

as the first bit received. The transmit routine should take this

requirement into account.

SCLK

TxD

80C51

SYNC

P1.1

SDIN

RxD

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5429/AD5439/

AD5449*

Figure 51. 80C51/80L51-to-AD5429/AD5439/AD5449 Interface

MC68HC11-to-AD5429/AD5439/AD5449 Interface

Figure 52 is an example of a serial interface between the DAC

and the MC68HC11 microcontroller. The SPI on the MC68HC11

is configured for master mode (MSTR) = 1, clock polarity bit

(CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is configured

by writing to the SPI control register (SPCR); see the MC68HC11

user manual. The SCK of the MC68HC11 drives the SCLK of

the DAC interface; the MOSI output drives the serial data line

(SDIN) of the AD5429/AD5439/AD5449.

SCLK

SCK

AD5429/AD5439/

AD5449*

SYNC

PC7

SDIN

MOSI

MC68HC11*

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 52. MCH68HC11/68L11-to-AD5429/AD5439/AD5449 Interface

The SYNC signal is derived from a port line (PC7). When data

is being transmitted to the AD5429/AD5439/AD5449, the SYNC

line is taken low (PC7). Data appearing on the MOSI output is

valid on the falling edge of SCK. Serial data from the 68HC11

is transmitted in 8-bit bytes with only eight falling clock edges

occurring in the transmit cycle. Data is transmitted MSB first.

To load data to the DAC, leave PC7 low after the first eight bits

are transferred and perform a second serial write operation to

the DAC. PC7 is taken high at the end of this procedure.

If the user wants to verify the data previously written to the input

shift register, the SDO line can be connected to MISO of the

MC68HC11, and, with SYNC low, the shift register clocks data

out on the rising edges of SCLK.

MICROWIRE-to-AD5429/AD5439/AD5449 Interface

Figure 53 shows an interface between the DAC and any

MICROWIRE-compatible device. Serial data is shifted out

on the falling edge of the serial clock, SK, and is clocked into

the DAC input shift register on the rising edge of SK, which

corresponds to the falling edge of the DAC SCLK.

SCLK

MICROWIRE*

SYNC

SDIN

AD5429/AD5439/

AD5449*

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 53. MICROWIRE-to-AD5429/AD5439/AD5449 Interface

PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the clock polarity bit (CKP) = 0. This is

done by writing to the synchronous serial port control register

(SSPCON). See the PIC16/17 microcontroller user manual for

more information. In this example, the I/O port, RA1, is used to

provide a SYNC signal and enable the serial port of the DAC. This

microcontroller transfers only eight bits of data during each serial

transfer operation; therefore, two consecutive write operations

are required. Figure 54 shows the connection diagram.

SCLK

SCK/RC3

PIC16C6x/7x*

SYNC

RA1

SDIN

SDI/RC4

AD5429/AD5439/

AD5449*

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 54. PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface

AD5429 Datasheet(PDF) 23 Page - Analog Devices

AD5429 Datasheet(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL