UP9506 datasheet(13/49 Pages) UPI

13 / 49 page

uP9506

uP9506-DS-F00A0, Jul. 2018

www.upi-semi.com

Functional Description

External MOSFET Driver Control

The DRCTRL pin is used for controlling the enable/disable

of external MOSFET drivers. Make sure to connect a 10k

Ω

resistor from this pin to GND and place this resistor close

to the controller. This resistor is used to generate the

reference current for thermal sense by TSENSE and

TSENSEA. Do not use any other resistance value. This

10k

Ω resistor must still be connected between DRCTRL to

ground even if external MOSFET driver is unused. Connect

this pin to a resistor R

ISO and then connect to the enable

control pin of the external MOSFET drivers as shown in

Figure 5. The recommended resistance value of R

ISO is

between 1k

Ω to 10kΩ. The DRCTRL is a noise sensitive

pin, therefore the PCB trace routing should be kept away

from other nets, especially the switching signals. It is

required to keep at least 20mil space to other nets.

10kohm

DRCTRL

RISO

To MOSFET

Driver Enable Pin

Noise sensitive. Keep trace

routing away from other nets.

Figure 5. DRCTRL Connection

PWM On Time Setting

The PWM on-time is set by an external resistor R

TON

connected between TONSET pin and GND. The controller

senses VINSEN voltage to obtain input voltage information

for PWM on-time calculation. Both the Vcore rail and VccGT

rail share the same PWM on-time setting. The PWM on-

time can be calculated as below equation.

100

)

(

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

TON

OUT

Table 4 lists the switching frequency and the recommended

resistor R

TON value (with condition: VIN = 12V, VOUT = 1.2V).

For example, given V

IN = 12V, VOUT = 1.2V, RTON = 50kΩ,

ON is about 500ns by above equation. The PWM frequency

is about 200kHz. Note that the resistance value of R

TON

value must be greater than 10k

Ω to ensure the PWM on-

time calculation circuit in normal operation.

Table 4. Switching Frequency and Resistor RTON

)

(

Ω

Ω )

Ω.

Soft Start

The slew rate of output voltage during soft start operation

and dynamic VID voltage change is determined internally.

Place a MLCC C

DAC between DAC and FBRTN (DACA and

FBRTNA for VccGT). The recommended capacitance of C

DAC

is 10nF. The slew rate during soft start operation is always

slow for non-zero Vboot case. The slow slew rate is

determined by the processor in SVID register 2Ah. The

fast slew rate can be further programmed by SMBus register

0x1Ch.

Dynamic VID Change and Slew Rate

The controller accepts SetVID command via SVID bus for

output voltage change during normal operation. This allows

the output voltage to change while the DC/DC converter is

running and supplying current to the load. This is commonly

referred to as VID on-the-fly (VID OTF). A VID OTF event

may occur under either light or heavy load condition. This

voltage change direction can be upward or downward. Per

SetVID command, the slew rate can be fast or slow. The

slow slew rate is determined by the SVID register 2Ah,

which can only be programmed by the processor. The

default value of slow slew rate is 1/2 of fast slew rate. The

fast slew rate of Vcore and VccGT can be separately further

programmed by the controllers SMBus register 0x1Ch. The

fast slew rate can be set from 12mV/us to 33mV/us with a

total of 7 steps and 3mV/LSB resolution. The default value

of fast slew rate is 12mV/us.

Output Voltage Differential Sense

The uP9506 uses differential sense by a high-gain low-

offset error amplifier for output voltage differential sense as

shown in Figure 6. The CPU voltage is sensed by the FB

and FBRTN pins (FBA and FBRTNA for VccGT). FB pin is

connected to the positive remote sense pin VCC_SENSE

of the CPU via the resistor R

FB. FBRTN pin is connected to

the negative remote sense pin VSS_SENSE of CPU

directly. (VCCGT_SENSE and VSSGT_SENSE for

VccGT). The error amplifier compares the V

FB with VEAP (=

DAC - ICSN x RDRP) to regulate the output voltage.

RCOMP

SMBus

COMP

ICSN

RFB

VCC_SENSE

Positive voltage remote

sense pin of CPU

CSP

CSN

EAP

DAC

RDRP

FBRTN

CDAC

VSS_SENSE

Negative voltage remote

sense pin of CPU

CCOMP

RCSN

CCSN

Reference

Voltage

Figure 6. Output Voltage Differential Sense

Total Load Current Sense

The uP9506 uses a low input offset current sense amplifier

(CSA) to sense the total load current flowing through

inductors for droop function by CSP and CSN (CSPA and

CSNA for VccGT) as shown in Figure 7.

UP9506 Datasheet(PDF) 13 Page - uPI Group Inc.

UP9506 Datasheet(HTML) 13 Page - uPI Group Inc.

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